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quad adc with diagnostics data sheet adau1977 rev. a document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or paten t rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 ? 2013 analog devices, inc. all rights reserved. technical support www.analog.com features programmable mic rophone bias (5 v to 9 v) with diagnostics four 10 v rms capable direct - coupled differential inputs on - chip pll for master clock low emi design 1 0 6 db adc dynamic range ? 9 5 db thd + n selectable digital high - pass filter 24 - bit adc with 8 khz to 192 khz sample rates digital volume control with autoramp function i 2 c/ spi control software - controllable clickless mute software power - down right justified, left justified, i 2 s justified , and tdm modes master and slave operation modes 40 - lead l fcs p package qualified for automotive applications applications automotive audio systems active noise cancellation system general description the adau1977 incorporates four high performance analog - to - digital converters (adcs) with direct - coupled inputs capable of 10 v rms. the adc uses multibit sigma - delta ( - ) architecture with continuous time front end for low emi . the adcs can be connected to the electret microphone ( ecm ) directly and pro - vide the bias for powering the microphone . b uilt - in diagnostic circuitry detects fault s on input lines and includes comprehensive diagn ostics for faults on microphone inputs . the faults reported are short to battery , short to microphone bias , short to ground, short between positive and negative input pins , and open input terminals. in addition, each diagnostic fault is available as an irq flag for ease in system design. an i 2 c/spi control port is also included. the adau1977 uses only a single 3 .3 v supply . the part internally g enerates the m icrophone bias voltage . the microphone bias is programmable in a few steps from 5 v to 9 v . the low power architecture reduces the power consumption. an o n - chip pll can derive the master clock from an external c lock input or frame clock (sample rate clock). when fed with a frame clock , the pll eliminates the need for a separate high frequency master clock in the system . the adau 1977 is available in a 40 - lead lfcsp package. functional block dia gram figure 1. micbias mb_gnd diagnostics ain1 p vboost_in vboost_out scl/cclk sda/cout addr1/cin addr0/cl a tch f au l t pd/rst ain1n ain2 p ain2n ain3 p ain3n ain4 p ain4n vba t a vddx a vdd2 agndx bg ref a ttenu a t or 14db programmable gain decim a t or/hpf dc calibr a tion i2c/spi contro l seria l audio port 5v t o 9v prog bias sw vba t vref mclkin pll_fi l t a vdd1 a vdd3 a vdd2 dgnd agnd3 agnd2 agnd1 pgnd sa_mode pll agnd2 pgnd dvdd iovdd lrclk bclk sdat aout1 sdat aout2 boost converter i out 50m a 3.3v t o 1.8v regul a t or adau1977 10296-001 adc adc adc adc agnd1 agnd2 agnd3 a vdd1 a vdd3
adau1977 data sheet rev. a | page 2 of 64 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general description ......................................................................... 1 functional block diagram .............................................................. 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 analog performance specifications ........................................... 3 diagnostic and fault specifications ........................................... 4 digital input/output specifications ........................................... 5 power supply specifications ........................................................ 5 digital filters specifications ....................................................... 6 timing specifications .................................................................. 7 absolute maximum ratings ............................................................ 9 ther mal resistance ...................................................................... 9 esd caution .................................................................................. 9 pin configuration and function descriptions ........................... 10 typical performance characteristics ........................................... 12 theory of operation ...................................................................... 14 overview ...................................................................................... 14 power supply and voltage reference ....................................... 14 power - on reset sequence ........................................................ 14 pll and clock ............................................................................. 15 dc - to - dc boost converter ...................................................... 16 microphone bias ......................................................................... 17 analog inputs .............................................................................. 17 adc ............................................................................................. 21 adc summing modes .............................................................. 21 diagnostics .................................................................................. 21 serial audio data output ports data format ..................... 23 control ports ................................................................................... 28 i 2 c mode ...................................................................................... 29 spi mode ..................................................................................... 32 register summary .......................................................................... 34 register details ............................................................................... 35 master power and soft reset register ..................................... 35 pll control register ................................................................. 36 dc - to - dc boost converter control register ....................... 37 micbias and boost control register .................................... 38 block power control and serial port control register ......... 39 serial port control register1 .................................................... 40 serial port control register2 .................................................... 41 channel mapping for output serial ports register ............... 42 channel mapping for output serial ports register ............... 44 serial output drive and overtemperature protection control register ......................................................................... 46 post adc gain channel 1 control regist er .......................... 47 post adc gain channel 2 control register .......................... 48 post adc gain channel 3 control register .......................... 49 post adc gain channel 4 control register .......................... 50 high - pass filter and dc offset control register and master mute ................................................................................ 51 diagnostics control register .................................................... 52 diagnostics report register channel 1 .................................. 53 diagnostics report register channel 2 .................................. 54 diagnostics report register channel 3 .................................. 55 diagnostics report register channel 4 .................................. 56 diagnostics interrupt pin control register 1 ......................... 57 diagnostics interrupt pin control register 2 ......................... 58 diagnostics adjustments register 1 ........................................ 59 diagnostics adjustments register 2 ........................................ 60 adc clipping status register .................................................. 61 digital dc high - pass filter and calibration register .......... 62 applications circuit ....................................................................... 63 outline dimensions ....................................................................... 64 ordering guide .......................................................................... 64 automotive products ................................................................. 64 revision history 3/13 rev. 0 to rev. a changed cp - 40- 9 to cp - 40- 14 ......................................... universal changes to hysteresis ainxp and ainxn shorted together p arameter, table 2 .............................................................................. 4 changes to thermal resistance section and table 8 .................... 9 changes to spi mode section ........................................................ 32 changes to channel mapping for output serial ports register section and table 34 ....................................................................... 44 changes to figure 46 ....................................................................... 63 changes to ordering guide ........................................................... 64 1 /1 3 revision 0: initial version
specifications performance of all channels is identical, exclusive of the interchannel gain mismatch and interchannel phase deviation specif ications. av dd x /iovdd = 3.3 v; dvdd (internally generated) = 1.8 v; vbat = 14.4 v; t a = ?40c to +105c, unless otherwise noted; master clock = 12.288 mhz (48 khz f s , 256 f s mode); input sample rate = 48 khz; measurement bandwidth = 20 hz to 20 khz; word width = 24 bits; load capacitance ( digital output) = 20 pf; load current (digital output) = 1 ma; digital input voltage high = 2.0 v; digital input voltage low = 0.8 v. analog performance s pecifications table 1 . parameter test conditions /comments min typ max unit line input application see figure 46 full - scale differential input voltage dc - coupled, v cm at ainxp/ainxn = 7 v 10 v rms full - scale single - ended input voltage dc - coupled, v cm at ainxp /ainxn = 7 v 5 v rms microphone input application see figure 46 , micbias = 8.5 v differential input voltage dc - coupled, v cm at ainxp = 5.66 v , ainxn = 2.83 v 2 v rms quasi dc input single - ended input voltage 5 v peak input co mmon - mode voltage v cm at ainxp/ainxn pins 0 8 v dc peak input voltage v cm + v ac p ea k at ainxp/ainxn pins 0 14 v microphone bias output voltage programmable from 5 v to 9 v in steps of 0.5 v ; the output voltage is within the specified load regulation 5 9 v load regulation from no load to maximum load of 25 ma at 5 v ? 1 + 0.2 + 1 % from no load to maximum load of 45 ma at 9 v ? 1 + 0.3 +1 % output current at micbias = 5 v 25 ma at micbias = 9 v 45 ma output noise 20 hz to 20 khz , micbias = 5 v 22 32 v rms 20 hz to 20 khz, micbias = 9 v 35 54 v rms power supply rejection ratio (psrr) 350 mv rms , 1 k hz ripple on vboost _ in at 10 v 60 db interchannel isolation at micbias pin referred to full scale at 1 k hz 60 db start - up time with c load = 1 nf 40 ms boost converter input voltage 2.97 3.3 3.63 v input current l = 4.7 h, f sw = 1.536 mhz, micbias = 9 v at 45 ma load 195 ma l = 2.2 h, f sw = 3 . 072 mhz, micbias = 9 v at 45 ma load 220 ma output current micbias = 5 v 50 ma micbias = 9 v 88 ma load regulation from no load to maximum load of 50 ma at micbias = 5 v ? 1 +1 % from no load to maximum load of 88 ma at micbias = 9 v ? 1 +1 % input overcurrent threshold 900 ma p ea k switching frequency f s = 48 k hz l = 2.2 h 3.072 mhz f s = 48 k hz , l = 4 . 7 h 1.5 36 mhz external load capacitor at vboost _out pin 4.7 10 22 f analog - to - digital converters input resistance differential between ainxp and ainxn 5 0 k? single - ended (rin 1977 ) between ainxp and ainxn 25 k? adc resolution 24 bits dynamic range (a - weighted ) 1 input = 1 khz , ? 60 db fs line input referred to full - scale differential input = 10 v rms 103 106 db microphone input referred to full - scale differential input = 2 v rms 92 db total harmonic distortion plus noise (thd + n) input = 1 khz, ?1 dbfs (0 dbfs = 10 v rms input) ? 95 ? 89 db digital gain post adc gain step size = 0.375 db ? 35.625 + 60 db gain error ? 10 +10 % interchannel gain mismatch ? 0.25 +0.25 db
adau1977 data sheet rev. a | page 4 of 64 parameter test conditions /comments min typ max unit gain drift 0.6 ppm/c common - mode rejection ratio ( cmrr ) 1 v rms, 1 khz 60 db 1 v rms, 20 khz 56 db power supply rejection ratio (psrr) 100 mv rms, 1 khz on avdd x = 3.3 v 70 db interchannel isolation 100 db inte r channel phase deviation 0 degrees reference internal reference voltage vref pin 1.47 1.50 1.54 v output impedance 20 k ? adc serial port output sample rate 8 192 khz 1 for f s ranging from 44.1 khz to 192 khz. diagnostic and fault specifications applicable to differential microphone input using micbias on ainxp and ainxn pins. table 2 . parameter test conditions / comments min typ max unit input voltage thresholds for fault detection 1 hysteresis ainxp or ainxn shorted to vbat sht_b_trip = 10 0.79 vbat 0.85 vbat 0.86 vbat v sht_b_trip = 01 0.84 vbat 0.9 vbat 0.91 vbat v sht_b_trip = 00 0.89 vbat 0.95 vbat 0.96 vbat v sht_b_trip = 11 0.93 vbat 0.975 vbat 0.99 vbat v hysteresis ainxp and ainxn shorted together sht_t_trip = 00 micbias(0.5 0.015 ) micbias(0.5 0.035 ) micbias(0.5 0.047 ) v sht_t_trip = 01 micbias(0.5 0.001 ) micbias(0.5 0.017 ) micbias(0.5 0.03 ) v sht_t_trip = 10 micbias(0.5 0.05 ) micbias(0.5 0.071 ) micbias(0.5 0.08 ) v hysteresis ainxp or ainxn shorted to ground sht_g_trip = 10 0.04 vref 0.1 vref 0.13 vref v sht_g_trip = 01 0.08 vref 0.133 vref 0.16 vref v sht_g_trip = 00 0.12 vref 0.2 vref 0.22 vref v sht_g_trip = 11 0.19 vref 0.266 vref 0.28 vref v hysteresis ainxp shorted to micbias sht_m_trip = 10 0.82 micbias 0.85 micbias 0.89 micbias v sht_m_trip = 01 0.87 micbias 0.9 micbias 0.94 micbias v sht_m_trip = 0 0 0.92 micbias 0.95 micbias 1.0 micbias v sht_m_trip = 1 1 0.95 micbias 0.975 micbias 1.0 micbias v hysteresis ainxp or ainxn open circuit 2 refer to the ainxp shorted to micbias and the ainxn shorted to ground specifications for upper and lower thresholds. fault duration programmable 10 100 150 ms 1 the threshold limits are tested with vref = 1.5 v , micbias = 5 v to 8.5 v , and vbat = 11 v to 18 v set using an external so urce. when vbat micbias, a short to vbat cannot be distinguished from a short to micbias, and reporting a short to vbat fault takes precedence over a short to micbias fault. 2 the ainxp open terminal fault cannot be distinguished from the ainxn open termin al fault because the voltage at the ainxp and ainxn pins remain at micbias and ground , respectively, when either of these two terminals becomes open circuit .
data sheet adau1977 rev. a | page 5 of 64 digital input/output specifications table 3 . parameter test conditions/comments min max unit input high level input voltage (v ih ) 0.7 iovdd v low level input voltage (v il ) 0.3 iovdd v input leakage current 10 a input capacitance 5 pf output high level output voltage (v oh ) i oh = 1 ma iovdd ? 0.60 v low level output voltage (v ol ) i ol = 1 ma 0.4 v power supply specification s l = 4.7 h, avdd x = 3.3 v, dvdd = 1.8 v, iovdd = 3.3 v , f s = 48 khz (master mode) , unless otherwise noted. table 4 . parameter test conditions/comments min typ max unit dvdd o n - chip ldo 1.62 1.8 1.98 v avdd x 3.0 3.3 3.6 v iovdd 1.62 3.3 3.6 v vbat 1 14.4 18 v iovdd current m aster clock = 256 f s normal operation f s = 48 khz 450 a f s = 96 khz 8 80 a f s = 192 khz 1.75 ma power - down f s = 48 khz to 192 khz 20 a a vdd x current normal operation boost off, 4 - channel adc, dvdd internal 14 ma boost on , 4 - channel adc, dvdd internal 14.5 ma boost off, 4 - channel adc, dvdd external 9.6 ma boost on, 4 - channel adc, dvdd external 10.1 ma power - down 2 7 0 a boost converter current normal operation boost on, 4 - channel adc, micbias = 8.5 v, no load 34 ma boost on, 4 - channel adc, micbias = 8.5 v, 42 ma 1 68 ma power - down 1 8 0 a dvdd current normal operation dvdd external = 1.8 v 4.5 ma power - down 65 a v bat current vbat = 14.4 v normal operation 5 75 625 a power - down 5 75 625 a power dissipation normal operation master clock = 256 f s , 48 khz avdd x dvdd internal, micbias = 8.5 v at 42 ma l oad 265 mw power - down, all supplies pd / rst pin held low 9 mw 1 when vbat micbias, a short to vbat cannot be distinguished from a short to micbias, and reporting a short to vbat fault tak es precedence over a short to micbias fault.
adau1977 data sheet rev. a | page 6 of 64 digital filters specifications table 5 . parameter mode factor min typ max unit adc decimation filter all modes, typ ical at f s = 48 khz pass band 0.4375 f s 21 khz pass - band ripple 0.015 db transition band 0.5 f s 24 khz stop band 0.5625 f s 27 khz stop - band attenuation 79 db group delay f s = 8 khz to 96 khz 22.9844/ f s 479 s f s = 192 khz 35 s high - pass filter all modes, typical at 48 khz cutoff frequency at ? 3 db point 0.9375 hz phase deviation at 20 hz 10 degrees settling time adc digital gain all modes 0 60 db gain step size 0.375 db
data sheet adau1977 rev. a | page 7 of 64 timing specification s table 6 . limit at parameter min max unit description input master clock (mclk) duty cycle 40 60 % mclkin duty cycle; mclkin at 256 f s , 384 f s , 512 f s , and 768 f s f mclk see table 10 mhz mclkin frequency, pll in mclk mode reset reset pulse 15 ns rst low pll lock time 10 ms i 2 c port f scl 400 khz scl frequency t sclh 0.6 s scl high t scll 1.3 s scl low t scs 0.6 s setup time; relevant for repeated start condition t sch 0.6 s hold time; after this period of time, the first clock pulse is generated t ds 100 ns data setup time t dh 0 data hold time t scr 300 ns scl rise time t scf 300 ns scl fall time t sdr 300 ns sda rise time t sdf 300 ns sda fall time t bft 1.3 s bus - free time; time between stop and start t susto 0.6 s setup time for stop condition spi port t ccph 35 ns cclk high t ccpl 35 ns cclk low f cclk 10 mhz cclk frequency t cds 10 ns cin setup to cclk rising t cdh 10 ns cin hold from cclk rising t cls 10 ns clatch setup to cclk rising t clh 40 ns clatch hold from cclk rising t clph 10 ns clatch high t coe 30 ns cout enable from clatch falling t cod 30 ns cout delay from cclk falling t cots 30 ns cout tristate from clatch rising adc serial port t abh 10 ns bclk high, slave mode t abl 10 ns bclk low, slave mode t als 10 ns lrclk setup to bclk rising, slave mode t alh 5 ns lrclk hold from bclk rising, slave mode t abdd 18 ns sdataoutx delay from bclk falling
adau1977 data sheet rev. a | page 8 of 64 figure 2. serial output port timing figure 3. spi port timing figure 4. i 2 c port timing bclk lrclk sdataoutx left justified mode sdataoutx right justified mode lsb sdataoutx i 2 s mode msb msb ? 1 msb msb 8-bit clocks (24-bit data) 12-bit clocks (20-bit data) 14-bit clocks (18-bit data) 16-bit clocks (16-bit data) t abl t abdd t abdd t abh t abdd t als t alh 10296-002 clatch cclk cin cout t cls t cds t cdh t cod t ccph t ccpl t clh t clph t coe t cots 10296-003 t sch t sclh t scr t scll t scf s d a scl t sch t scs t dh t sdf t sdr t ds stop start t susto t bft 10296-004
data sheet adau1977 rev. a | page 9 of 64 absolute maximum rat ings table 7 . parameter rating analog supply (avdd x ) ? 0.3 v to +3.6 3 v digital supply dvdd ? 0.3 v to +1.98 v iovdd ? 0.3 v to +3.6 3 v input current (except supply pins) 20 ma analog input voltage ( ainx, vbat pins ) ? 0.3 v to + 18 v digital input voltage (signal pins) ? 0.3 v to +3.6 3 v operating temperature range ( ambient ) ? 40c to +1 0 5c junction temperature range ? 40c to +125c storage temperature range ? 65c to +150c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal resistance ja represents thermal resistance, junction - to - ambient, and jc represents the thermal resistance, junction - to - case. all characteristics are for a standard jedec board per jesd51. table 8 . thermal resistance package type ja jc unit 40 - lead l fcsp 32.8 1.93 c/w esd caution
adau1977 data sheet rev. a | page 10 of 64 pin configuration an d function descripti ons figure 5 . pin configuration, 4 0- lead l fcsp table 9 . pin function descriptions pin no. mnemonic in/out 1 description 1 agnd1 p analog ground. 2 vref o voltage reference. decouple this pin to agndx with 10 f||100 nf capacitors. 3 pll_filt o pll loop filter. return this pin to avddx using recommended loop filter components. 4 avdd2 p analog power supply. connect this pin to analog 3.3 v supply. 5 agnd2 p analog ground. 6 pd / rst i power - down reset (active low). 7 mclkin i master clock input. 8 fau lt o fault output. programmable logic output. 9 sa_mode i standalone mode. connect this pin to iovdd using a 10 k ? pull - up resistor for standalone mode. 10 dvdd o 1.8 v digital power supply output. decouple this pin to dgnd with a 0.1 f capacitor. 11 dgnd p digital ground. 12 iovdd p digital input and output power supply. connect this pin to a supply in the range of 1.8 v to 3.3 v. 13 sdataout1 o adc serial data output pair 1. 14 sdataout2 o adc serial data output pair 2. 15 lrclk i/o frame clock for the adc serial port. 16 bclk i/o bit clock for the adc serial port. 17 sda/cout i/o serial data output i 2 c/control data output (spi). 18 scl/cclk i serial clock input i 2 c/control clock input (spi). 19 addr0/ clatch i chip address bit 0 setting i 2 c/chip select input for control data (spi). 20 addr1/cin i chip address bit 1 setting i 2 c/control data input (spi). 21 pgnd p power ground boost converter. 22 pgnd p power ground boost converter. 23 sw i inductor switching terminal. 24 sw i inductor switching terminal. 25 vboost_out o boost converter output. decouple this pin to pgnd with a 10 f capacitor. 26 vboost_in i micbias regulator input. connect this pin to vboost_out (pin 25). 27 micbias o microphone bias output. decouple this pin to agndx using a 10 f capacitor. 28 mb_gnd p analog return ground for the microphone bias regulator. connect this pin directly to agndx for best noise performance. 29 agnd3 p analog ground. 30 vbat i voltage sense for diagnostics. connect this pin to a load dump suppressed battery voltage. decouple this to agndx using a 0.1 f capacitor. pin 1 indic a t or 1 agnd1 2 vref 3 pll_fi l t 4 a vdd2 5 agnd2 6 pd/rst 7 mclkin 8 f au l t 9 sa_mode notes 1. the exposed p ad must be connected t o the ground plane on the pcb. 10 dvdd 23 sw 24 sw 25 vboost_out 26 vboost_in 27 micbias 28 mb_gnd 29 agnd3 30 vb a t 22 pgnd 21 pgnd 1 1 dgnd 12 iovdd 13 sdat aout1 15 lrclk 17 sda/cout 16 bclk 18 scl/cclk 19 addr0/cl a tch 20 addr1/cin 14 sdat aout2 33 ain1 p 34 ain2n 35 ain2 p 36 ain3n 37 ain3 p 38 ain4n 39 ain4 p 40 a vdd1 32 ain1n 31 a vdd3 t o p view (not to scale) adau1977 10296-005
data sheet adau1977 rev. a | page 11 of 64 pin no. mnemonic in/out 1 description 31 avdd3 p analog power supply. connect this pin to an analog 3.3 v supply. 32 ain1n i analog input channel 1 inverting input. 33 ain1p i analog input channel 1 noninverting input. 34 ain2n i analog input channel 2 inverting input. 35 ain2p i analog input channel 2 noninverting input. 36 ain3n i analog input channel 3 inverting input. 37 ain3p i analog input channel 3 noninverting input. 38 ain4n i analog input channel 4 inverting input. 39 ain4p i analog input channel 4 noninverting input. 40 avdd1 p analog power supply. connect this pin to an analog 3.3 v supply. ep exposed pad. the exposed pad must be connected to the ground plane on the printed circuit board (pcb). 1 i = input, o = output, i/o = input/output, and p= power.
adau1977 data sheet rev. a | page 12 of 64 typical performance characteristics figure 6. fast f ourier t ransform, 2 mv differential input at f s = 48 khz figure 7. fast fourier transform, ? 1 dbfs differential input figure 8 . thd + n vs. input amp litude figure 9 . cmrr differential input , referenced to 1 v differential input figure 10 . fast fourier transform, no in put figure 11 . adc pass - band ripple at f s = 48 khz 2 0 20 4 6 8 10 12 14 16 18 ?160 0 ?150 ?140 ?130 ?120 ?1 10 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 frequenc y (khz) amplitude (dbfs) 10296-006 2 0 20 4 6 8 10 12 14 16 18 frequenc y (khz) amplitude (dbfs) ?160 0 ?150 ?140 ?130 ?120 ?1 10 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 10296-007 0 2 12 4 6 input amplitude (v rms) thd + n (db) 8 10 ?160 0 ?150 ?140 ?130 ?120 ? 1 10 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 10296-008 ?100 0 ?95 ?90 ?85 ?80 ?75 ?70 ?65 ?60 ?55 ?50 ?45 ?40 ?35 ?30 ?25 ?20 ?15 ?10 ?5 20k 20m 100k 1m cmrr (db) frequenc y (hz) 10m 10296-009 0 2 20 4 6 8 10 12 14 16 18 frequenc y (khz) amplitude (dbfs) ?160 0 ?150 ?140 ?130 ?120 ? 1 10 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 10296-010 0.10 0.08 0.06 0.04 0.02 0 ?0.10 ?0.08 ?0.06 ?0.04 ?0.02 0 18000 16000 14000 12000 10000 8000 6000 4000 2000 magnitude (db) frequency (hz) 10296-0 1 1
data sheet adau1977 rev. a | page 13 of 64 figure 12 . adc filter stop - band response at f s = 48 khz 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 0 40000 5000 10000 15000 20000 25000 30000 35000 magnitude (db) frequency (hz) 10296-012
adau1977 data sheet rev. a | page 14 of 64 theory of operation overview the adau1977 incorporates four high performance adcs with an integrated boost converter for microphone bias, the associated microphone diagnostics for fault detection, and a phase - locked loop circuit for generating the necessary on - chip clock signals. power s upply and voltage re ference the adau1977 requires a single 3.3 v power supply. separate power supply input pins are provided for the analog and b oost converter. these pins should be decoupled to a gnd with 100 nf ceramic chip capacitors placed as close as possible to the pins to minimize noise pickup. a bulk aluminum electrolytic capacitor of at least 10 f must be provided on the same pcb as the ad c. it is important that the analog supply be as clean as possible for best performance. the supply voltage for the digital core (dvdd) is generated using an internal low dropout regulator. the typical dvdd output is 1.8 v and must be decoupled using a 100 nf ceramic capacitor and a 10 f capacitor. place the 100 nf ceramic capacitor as close as possible to the dvdd pin. the voltage reference for the analog blocks is generated internally and output at the vref pin ( pin 2 ). the typical voltage at the pin is 1.5 v with an av dd x of 3.3 v. all digital inputs are compatible with ttl and cmos levels. all outputs are driven from the iovdd supply. the iovdd can be in the range of 1.8 v to 3.3 v. the iovdd pin must be decoupled with a 100 nf capacitor placed as close to the iovdd pin as possible. it is recommended to connect the agnd, dgnd, pgnd, and exposed pad to a single gnd plane on the pcb for best performance. the adc internal voltage reference is output from the vref pin and s hould be decoupled using a 100 nf ceramic capacitor in parallel with a 10 f capacitor. the vref pin has limited current capability. the voltage reference is used as a reference to the adc ; therefore, it is recommended not to draw current from this pin for external circuits . when us ing this reference, use a noninverting amplifier buffer to provide a reference to other circuits in the application. in reset mode , the vref pin is disabled to save power and is enabled only when the rst pin is pulled high. power - on reset sequence the adau1977 requires that a single 3.3 v power supply be provided externally at the av dd x pin. the part in ternally generates dvdd (1.8 v) , which is used for the digital core of the adc. the dvdd supply output pin ( pin 10) is provided to connect the decoupling capacitors to dgnd . the typical recommended values for the decoupling capacitor s are 100 nf in paralle l with 10 f. during a reset, the dvdd regulator is disabled to reduce power consumption. after the pd / rst pin ( pin 6) is pulled high , the part enable s the dvdd regulator. however , the internal adc and digital core reset is controlled by the internal por signal ( power - on reset ) circuit , which monitors the dvdd level. therefore, the device does not come out of a reset until dvdd reaches 1.2 v and the por signal is released. the dvdd settling time depend s on the charge - up time for the external capacitors and on the avdd x ramp - up time. the internal por circuit is provided with hysteresis to ensure that a reset of the part is not initiated by an instantaneous glitch on dvdd. the typical trip points are 1.2 v with rst high and 0.6 v ( 20%) with rst low. this ensures that the core is not reset until the dvdd level falls below the 0.6 v trip point. as soon as the pd / rst pin is pulled high, the internal regulator starts charging up the c ext on the dvdd pin. the dvdd charge - up time is based on the output resistance of the regulator and the external decoupling capacitor. the time constant can be calculated as t c = r out c ext ( r out = 20 ? typical) for example, if c ext is 10 f , then t c is 200 s and is t he time to reach the dvdd voltage , within 63.6%. the por circuit releases an internal reset of the core when dvdd reaches 1.2 v (s ee figure 13) . therefore, it is recommended to wait for at least the t c period to elapse before sending i 2 c or spi control signals. figure 13 . power - on reset timing when applying a hardware reset to the part by pulling the pd / rst pin ( pin 6) low and then high , there are certain time restrictions. during the rst low pulse period , the dvdd star ts discharging. the discharge time constant is decided by the internal re sistance of the regulator and c ext . the time required for dvdd to fall from 1.8 v to 0.48 v (0.6 v ? 20%) can be estimated using the following equation: t d = 1.32 r int c ext where r int = 64 k ? typical. (r int can vary due to process by 20% . ) for example, if c ext is 10 f , then t d is 0.845 sec . 1.2v 0.48v por dvdd (1.8v) pd/rst avddx t reset t d t c 10296-013
data sheet adau1977 rev. a | page 15 of 64 depending on c ext , t d may var y and in turn decide the minimum hold period for the rst pulse. the rst pulse must be held low for the t d time period to initialize the core properly. the required rst low pulse period can be reduced by adding a resistor across c ext . the new t d value can then be calculated as t d = 1.32 r eq c ext where r eq = 64 k ? || r ext . the resistor ensure s that dvdd not only discharges quickly during a reset or an av dd x power loss but also reset s the internal blocks correctly. n ote that some power loss in this resistor is to be expected because the resistor constantly draws current from dvdd. the typical value for c ext is 10 f and for r ext is 3 k ? . this results in a time constant of t d = 1.32 r eq c ext = 37.8 ms where r eq = 2.866 k ? ( 64 k ? || 3 k ? ). using this equation at a set c ext value, the r ext can be calculated for a desired rst pulse period. there is also a software reset register (s_rst, bit 7 of register 0x00) available that can be used to reset the part , but it must be noted that during an av dd x power loss, the software reset may not ensure proper initialization because dvdd may not be stable. figure 14 . dvdd regulator output connections pll and cloc the adau1977 has a built - in analog pll to provide a jitter - free master clock to the internal adc. the pll must be programmed for the appropriate input clock frequency. the pll control register 0x01 is used for setting the pll. the clk_s bit (bit 4) of register 0x01 is used for setting the clock source for the pll. the clock source can be either the mclk in pin or the lrclk pin ( slave mode ) . in lrclk mode , the pll can support sample rates between 32 k hz and 192 khz. in mclk input mode , the mcs bits (bits [2:0] of register 0x01 ) must be set to the desired input clock frequency for the mclkin pin. table 10 shows the input mclk required for the most common sample rates and the mcs bit settings. the pll_lock bit (bit 7 ) of register 0x01 indicates the lock status of the pll. it is recommended that after initial power - up the pll lock status be read to ensure tha t the pll outputs the correct frequency before unmuting the audio outputs. table 10. required input mclk for common sample rates mcs (bits[2:0]) f s (khz) frequency multi - plication ratio mclkin frequency (mhz) 000 32 128 f s 4.096 001 32 256 f s 8.192 010 32 384 f s 12.288 011 32 512 f s 16.384 100 32 768 f s 24.576 000 44.1 128 f s 5.6448 001 44.1 256 f s 11.2896 010 44.1 384 f s 16.9344 011 44.1 512 f s 22.5792 100 44.1 768 f s 33.8688 000 48 128 f s 6.144 001 48 256 f s 12.288 010 48 384 f s 18.432 011 48 512 f s 24.576 100 48 768 f s 36.864 000 96 64 f s 6.144 001 96 128 f s 12.288 010 96 192 f s 18.432 011 96 256 f s 24.576 100 96 384 f s 36.864 000 192 32 f s 6.144 001 192 64 f s 12.288 010 1 92 96 f s 18.432 011 192 128 f s 24.576 100 192 192 f s 36.864 the pll can accept the audio frame clock ( sample rate clock) as input , but the serial port must be configured as a slave and the frame clock must be fed to the part from the master. it is strongly recommended that the pll be disabled, reprogrammed with the new setting, and then re enabled. a lock bit is provided that can be polled via the i 2 c to check whether the pll has acquired lock. the pll requires an external filter , which is connected at the pll_filt pin ( pin 3 ). the recommended pll filter circuit for mclk or lrclk mode is shown in figure 15. using npo capacitors is recommended for temperature stability . place the filter components close to the device for best performance. figure 15 . pll filter 3.3v to 1.8v regulator dvdd adau1977 iovdd +1.8v or +3.3v c 0.1f c 0.1f c ext 10f mlcc x7r r ext 3k? avdd1 avdd3 avdd2 +3.3v to internal blocks 10296- 1 14 a vddx pll_lf lrclk mode 39nf 4.87k? 2.2nf a vddx pll_lf mclk mode 5.6nf 1k? 390pf 10296-014
adau1977 data sheet rev. a | page 16 of 64 dc - to - dc boost converter the boost converter generates a supply voltage for the microphone bias circuit from a fixed 3.3 v supply. the boost converter output voltage is programmable using register 0x03. the boost converter output voltage is approximately 1 v above the set microphone bias voltage. the boost converter uses the clock from the pll , and the switching frequency is dependent on the sample rate of the adc. the fs_rate bits ( bit s [6:5] of register 0x02 ) must be set to the desired sample rate. the boost converter switching frequency can be selected to be 1.5 mhz or 3 mhz using bit 4 of regi ster 0x02. for the 1.5 mhz switching frequency , t he recommended value for the inductor is 4.7 h , whereas for the 3 mhz switching frequency, the recommended value for the inductor is 2.2 h. table 12 lists the typical switching frequency based on the sample rates. inductor selection for the boost converter to operate efficiently , the inductor selection is critical. the two most important parameters for the inductor are the saturation current rating and the dc resistance. the recom - mended saturation rating for the inductor must be >1 a. the dc resistance affects the efficiency of the boost converter. assuming that the board trace resistances are negligible for 80% efficiency , the dc resistance of the inductor should be less than 50 m ? . table 11 lists some of the recommended inductors for the application. table 11. recommended inductors 1 value manufacturer manufacturer part number 2.2 h w rth ele k troni k 7440 430022 4.7 h w rth elektronik 7440530047 1 check with the manufacturer for the appropriate temperature ratings for a given application. the boost converter has a soft start feature that prevents inrush current from the input source. the boost converter has built - in over current and overtemperature protection. the input current to the boost converter is monitored and if it exceeds the set current threshold for 1.2 ms, the boost converter shut s down. the fault condition is recorded into register 0x02 and asserts the fault interrupt pin. this condi tion is cleared after reading the boost_ov bit (bit 2 ) or the boost_oc bit (bit 0 ) in register 0x02. the overcurrent protection bit, oc_en (b it 1 ), or the overvoltage protection bit, ov_en (b it 3 ), is on by default , and it is recommended not to disable the bit . each protection circuit ha s two modes for recovery after a fault event : autorecovery and manual recovery. the recovery mode can be selected using bit 0 of register 0x03. the autorecovery mode att empt s to enable the boost converter after a set recovery time , typically 20 ms. the manual recovery mode enable s the boost converter only if the user writ es 1 to the mrcv bit (bit 1 ) . if the fault persists , the boost converter remain s in shutdown mode until the fault is cleared. the boost converter is capable of supplying the 42 ma of total output current at the micbias output . the boost converter has overcurrent protection at the input ; the threshold is around 900 ma peak . ensure that the 3.3 v power supply feeding the boost converter has built - in overcurrent protection because there is no protection internal to adau1977 for a short circuit to any of the ground pin s (agnd/dgnd/pgnd) at the vboost_out or vboost_in pin. by default , the boost converter is disabled on power - up to allow the flexibility of connecting an external voltage source at the vboost_in pin to power the micro phone bias circuit. the boost converter can be enabled by using the boost_en bit (bit 2 of register 0x03 ) . capacitor selection the boost converter output is available at the vboost _ out pin ( pin 25 ) and must be decoupled to p gnd using a 10 f ceramic capacitor to remove the ripple at the switching frequency. the capacitor must have low esr and good temperature stability. the mlcc x7r /npo dielectric type with 25 v is recommended. c are must be taken to place this capacitor as close as possible to the v bo ost _out pin ( pin 25 ). table 12. typical switching frequency based on the sample rates boost converter switching frequency base sample rate (khz) sample rates (khz) inductor = 2.2 h inductor = 4.7 h 32 8 /16/32/64 (1024/1 2 ) f s (1024/22) f s 44.1 11.025/22.05/44.1/88.2/176.4 (1024/1 6 ) f s (1024/30) f s 48 12/24/48/96/192 (1024/16) f s (1024/32) f s
data sheet adau1977 rev. a | page 17 of 64 microphone bias the microphone bias is generated by the input voltage at the vboost_in pin (pin 26) via a linear regulator to ensure low noise performance and to reject the high frequency noise from the boost converter. if the internal boost converter output is used, the vboost_out pin (pin 25) must be connected to t he vboost_in pin (pin 26). if an external supply is used for the microphone bias, the supply can be fed at the vboost_in pin (pin 26); in this case, leave the vboost_out pin (pin 25) open. the microphone bias voltage is programmable from 5 v to 9 v by usin g the mb_volts bits (bits[7:4] of register 0x03). the microphone bias output voltage is available at the micbias pin (pin 27). this pin can be decoupled to agnd using a maximum of up to a 10 f capacitor with an esr of at least 1 ?. for higher value capacitors, especially those above 1 nf, the esr of the capa - citor should be 1 ? to ensure the stability of the microphone bias regulator. register 0x03 can be used to enable the microphone bias. table 12 lists the switching frequency of the boost converter based on the inductor value and common sample rates. analog inputs the adau1977 has four differential analog inputs. the adc s can accommodate both dc - and ac - coupled input signals. the block diagram shown in figure 16 represents the typical input circuit. in most audio applications, the dc content of the signal is removed by using a coupling capacitor. however , the adau1977 consist s of a unique input structure that allows direct coupling of the input signal , eliminating the need for using a large coupling capacitor at the input. each input has a fixed 14 d b attenuator connected to a gnd for accommodating a 10 v rms differential input. the typic al input resistance is approximately 26 k ? from each input to a gnd. in dc - coupled application s , if the v cm at ainxp and ainxn is the same , the dc content in the adc output is close to 0 . i f the input pins are presented with different common - mode dc level s, the difference between the two levels appear s at the adc output and can be removed by enabling the high - pass filter. the high - pass filter has a 1.4 hz, 6 db per octave cutoff at a 48 khz sample rate. the cutoff frequency scale s directly with the sample frequency. however , care is required in dc - coupled application s to ensure that the common - mode dc voltage does not exceed the specified limit. the common - mode loop can accommodate a common - mode dc voltage from 0 v to 7 v. the input required for the full - scale adc output (0 dbfs) is typically 10 v rms differential . figure 16 . analog input block v ref v x v y 2r ainx p ainxn v id = v input differentia l v icm+ = v cm a t ainx+ v icm? = v cm a t ainx? r 2r r r r r r 10296-015
adau1977 data sheet rev. a | page 18 of 64 line inputs th is section describes some of the possible ways to connect the adau1977 for line level inputs. line inp ut balanced or differential input dc - coupled case for example , in the case of a typical power amplifier for a n auto - mobile , the output can swing around 10 v rms differential with approximately 7.2 v common - mode dc input voltage ( assuming a 14.4 v battery and bridge - tied load connection ). the signal at each input pin has a 5 v rms or 14.14 v p - p signal swing . with a common - mode dc voltage of 7 .2 v, the signal can swing between (7 .2 v + 7 .07 v ) = +14 .2 7 v p - p and (7 v ? 7 .07 v ) = 0 .13 v at each input. therefore, this result s in approximately a 28. 5 4 v p - p differential signal swing and measure s around ? 0. 16 dbfs ( ac only with dc high - pass filter) at the adc output. see figure 17. line input ba lanced or differential input ac - coupled case for an amplifier output case with ac coupling , refer to figure 18 for information about connecting the line level inputs to the adau1977 . in this case , the ainxp/ainxn pins must be pulled up to the required common - mode level using the resistors on micbias. the v cm must be such that the input never swings below a ground . in other words , if the input signal is 14 v p - p , the v cm must be around 14 v/2 = 7 v to ensure that the signal never swings below a ground . the microphone bias can provide the required clean reference for generating the v cm . the r1 value can be calculated as follows : r1 = rin 1977 ( mb ? v cm )/ v cm w here : v cm is the peak - to - peak i nput s wing divided by 2 . mb = 8.5 v . rin 1977 is the single - ended input resistance (see table 1 ) . however , in this case the equivalent input resistance of ainxp/ ainxn is reduced and can be calculated as r1 || rin 1977 . input resistance = r1 rin 1977 /( r1 + rin 1977 ) w here rin 1977 is the single - ended value from table 1 . the c1 and c2 values can be determined for the required low frequency cutoff using the following equation : c1 or c2 = 1/(2 f c input resistance ) line input unbalanced or single - ended pseudo differential ac - coupled case for a single - ended application , the signal swing is reduced by half because only one input is used for the signal , and the other input is connected to 0 v. as a result, the input signal capability is reduced to 5 v rms in a sing le - ended application. with a common - mode dc voltage of 7.2 v , the signal can swing between (7.2 v + 7.07 v ) = +14.27 v p - p and (7.2 v ? 7 v ) = 0.13 v. therefore, this result s in approximately a 14.14 v p - p differe ntial signal swing and measure s around ? 6.16 dbfs ( ac only with dc high - pass filter) at the adc o utput. see figure 19. the value s of the resistor s ( r1/r2 ) and capacitors ( c 1/c2 ) are similar to those for the balanced ac - coupled case described in the line input balanced or differential input ac - coupled case section . line input unbalanced or single - ended ac - coupled case for a single - ended application, the signal swing is reduced by half because only one input is used for the signal, and the other input is connected to 0 v. as a result, the input signal capability is re duced to 5 v rms in a single - ended application. with a common - mode dc voltage of 7.2 v, the signal can swing between (7.2 v + 7.07 v) = +14.27 v p - p and (7.2 v ? 7 v) = 0.13 v. therefore, this result s in approximately a 14.14 v p - p differential signal swin g and measure s around ?6.16 dbfs (ac only with dc high - pass filter) at the adc output. the difference in the common - mode dc voltage between the positive and negative input (7.2 v) would appear at the adc output if the signal was not high - pass filtered. see figure 20. the values of the resistor (r1) and capacitor (c1) are simil ar to those for the balanced ac - coupled case described in the line input balanced or differential input ac - coupled case section.
data sheet adau1977 rev. a | page 19 of 64 figure 17. connecting the line level inputsdifferential dc-coupled case figure 18. connecting the line level inputsdifferential ac-coupled case figure 19. connecting the line level inputspseudo differential ac-coupled case figure 20. connecting the line level inputssingle-ended ac-coupled case attenuator 14db ainx+ adau1977 ainx? v diff = 10v rms ac v cm = 7v dc typic a l a udio powe r amplifier output 10296-016 attenuator 14db ainx+ c1 c3 r1 r2 c2 adau1977 ainx? micbias v dif f = 10v rms ac 10296-017 typic a l audio power amplifier output attenuator 14db ainx+ c1 c3 r1 r2 c2 adau1977 ainx? micbias v in = 5v rms ac 10296-018 t ypic a laudio power amplifier output attenuator 14db ainx+ c1 c3 r1 adau1977 ainx? micbias v in = 5v rms ac 10296-019 t ypic a l audio power amplifier output
adau1977 data sheet rev. a | page 20 of 64 microphone inputs this section describes some ways to connect the adau1977 for microphone input applications. the micbias voltage and the bias resistor value depend on the ecm selected. the adau1977 can provide the micbias from 5 v up to 9 v in 0.5 v steps. in an application requiring multiple microphones, care must be taken not to exceed the micbias output current rating. ecm balanced or differential input dc-coupled case for example, in a typical ecm, the output signal swing depends on the micbias voltage. with a typical 8.5 v supply, the ecm can output a 2 v rms differential signal. the signal at each input pin has a 1 v rms or 2.8 v p-p signal swing. with a common-mode dc level of 2/3 micbias on the ainxp and 1/3 micbias on the ainxn pins, this results in around ?14 dbfs (ac only with dc high-pass filter) at the adc output because the input is 14 db below the full-scale input of 10 v rms differential. see figure 21. ecm pseudo differential input ac-coupled case for a typical mems ecm module, the output signal swing is low. with a typical 3.3 v supply, the ecm module can output a 2 v rms differential signal. the signal at the input pin has a 1 v rms or 2.8 v p-p signal swing. for this application, it is recommended to bias the input pins using resistors to 7 v dc, similar to the case described in the line input unbalanced or single-ended pseudo differential ac-coupled case section. see figure 22. figure 21. connecting the microphone inpu tsdifferential inpu t dc-coupled case figure 22. connecting the microphone inputspseudo differential input ac-coupled case att enuator 14db ainx+ r r adau1977 ainx? micbias v in = 2v rms ac differential v cm+ 2/3 micbias v cm? 1/3 micbias r = typical 300 ? to 500 ? microphone typical ecm module notes 1. the diagnostics feature is available. 10296-020 attenuator 14db ainx+ r2 r1 c3 adau1977 ainx? micbias v max = 5v rms ac v dd typic a l ecm w ith preamp module 10296-021 notes 1. the diagnostics f e ature is not available.
data sheet adau1977 rev. a | page 21 of 64 adc the adau1977 contains four - adc channels configured as two stereo pairs with configur able differential/single - ended inputs. the adc can operate at a nominal sample rate of 32 khz up to 192 khz. the adc s include on - board digital anti aliasing filters with 79 db stop - band attenuation and linear phase response. digital outputs are supplied thr ough two serial data output pins (one for each stereo pair) and a common frame clock (lrclk) and bit clock (bclk). alternatively, one of the tdm modes can be used to support up to 16 channels on a single tdm data line. with smaller amplitude input signals, a 10 - b it programmable digital gain compensation for an individual channel is provide d to scale up the output word to full scale. care must be taken to avoid over compensation (large gain compensation) , which leads to clipping and thd degradation in the adc . the adcs also have a dc - offset calibration algorithm to null the systematic dc offset of the adc. this feature is useful for dc measurement applications. adc summing modes the four adcs can be grouped into either a single stereo adc or a single mono adc to increase the signal - to - noise ratio ( snr ) for the application. t wo options are available: one option for summing two channels of the adc and an other option for summing all four channels of the adc. s umming is performed in the digital block. 2 - channe l summing mode when the sum_mode bits (bits [7:6] of register 0x0e) are set to 01 , the channel 1 and channel 2 adc data are combined and output from the sdataout1 pin . similarly, the channel 3 and channel 4 adc data are combined and output from the sdataout2 pin. as a result, the snr improve s by 3 db . for this mode , both channel 1 and channel 2 must be connected t o the same input signal source. similarly , channel 3 and channel 4 must be connected to the same input signal source. 4 - channel summing mod e when the sum_mode bits (bits[7:6] of register 0x0e) are set to 10, the channel 1 thr ough channel 4 adc data are combined and output from the sdataout1 pin. as a result, the snr improves by 6 db. for this mode, all four channels must be connected to the same input signal source. diagnostics the diagnostic s block monitors the input pins in real time and reports a fault as a n interrupt signal on the fault pin ( pin 8 ) , which triggers sending an interrupt request to an external controller . t he diagnostics status registers ( register 0x11 through register 0x14 ) for c hannel 1 thr ough c hannel 4 are also updated . r efer to the register map table ( table 25 ) an d the register details tables ( table 42, table 43 , table 44 , and table 45 ) for more infor - mation about the diagnostics register content . the diagnostics can be enabled or disabled for each channel using bits[3:0] of register 0x10. the diagnostics are provided only when micbias is enabled and the microphone is connected as recommended in the appropriate application circuit (see figure 21) . diagnostics reporting the diagnostics status is reported individually for each channel in register 0x11 through register 0x14. the faults listed in table 13 are reported on each input pin . table 13 . faults reported fault ainxp ainxn short to battery yes yes short to micbias yes no short to ground yes yes short between positive and negative inputs yes yes open input yes yes diagnostics adjustments short circuit to battery supply when a n input terminal is shorted to the battery , the voltage at the terminal approaches the battery voltage. any voltage higher than the set threshold is reported as a fault. the threshold can be set using the sht_b_trip bits, bits[1:0] of register 0x17 ( see table 14) . table 14. setting the short to battery threshold sht_b_trip (register 0x17, bits [ 1 : 0 ] ) short to battery threshold 00 0.95 vbat 01 0.9 vbat 10 0.85 vbat 11 0.975 vbat short circuit to micbias this feature is supported only on the ainxp terminal. when a n ainxp terminal is shorted to micbias, the voltage at the ainxp terminal approaches the micbias voltage. any voltage higher than the set threshold is reported as a fault. the threshold can be set using the sht_m_trip bits, bits[5:4] of register 0x17 (see table 15 ). table 15. setting the short to micbias threshold sht_m_trip (register 0x17, bits [5:4] ) short to micbias threshold 00 0.95 micbias 01 0.9 micbias 10 0.85 micbias 11 0.975 micbias short circuit to ground when a n input terminal is shorted to ground , the terminal voltage reaches close to 0 v. any voltage lower than the set threshold is reported as a fault. the threshold is referenced to vref and , therefore, scale s with the voltage at the vref pin.
adau1977 data sheet rev. a | page 22 of 64 the threshold can be set using the sht_g_trip bits, bits[3:2] of register 0x17 (see table 16). table 16. sht_g_trip (register 0x17, bits[3:2]) short to ground threshold 00 0.2 vref 01 0.133 vref 10 0.1 vref 11 0.266 vref microphone terminal short circuited when both input terminals are shorted, both the ainxp and ainxn input terminals are at the same voltagearound micbias/2. any voltage between the set thresholds is reported as a fault. the upper and lower threshold voltages can be set using the sht_t_trip bits, bits[7:6] of register 0x17 (see table 17). the following equations can be used to calculate the upper and lower thresholds: upper threshold = micbias (0.5 + x ) lower threshold = micbias (0.5 ? x ) where x can be set using the sht_t_trip bits, bits[7:6] of register 0x17 (see table 17). table 17. sht_t_trip (register 0x17, bits [7:6]) x 00 0.035 01 0.017 10 0.071 11 reserved microphone terminals open in the event that any of the input terminals becomes open circuited, ainxp is pulled to micbias and ainxn is pulled to a common ground. when the ainxp terminal is at a voltage that is higher than the short to the micbias threshold (set using bits[5:4] of register 0x17) and the ainxn terminal voltage is at a voltage that is less than the short to the ground threshold (set using bits[3:2] of register 0x17), a fault is reported. the fault cannot indicate which terminal is open circuited because any terminal that is open circuited pulls ainxp to micbias and ainxn to a common ground. fault pin the fault pin is an output pin that can be programmed to be active high or active low logic using the irq_pol bit (bit 4 of register 0x15). in addition, the fault pin can be set using the irq_drive bit (bit 5 of register 0x15) to drive always or to drive only during a fault and is otherwise set to high-z. the fault status is registered in the irq_reset bit (bit 6 of register 0x15). the irq_reset bit is a latched bit and is set in the event of a fault and cleared only after the fault status bit is read. fault timeout to prevent the false triggering of a fault event, the fault timeout adjust bits (bits[5:4] of register 0x18) are provided. these bits can be used to set the time that the fault needs to persist before being reported. the timeout can be set to 0 ms, 50 ms, 100 ms, or 150 ms using the fault_to bits (bits[5:4] of register 0x18). the default value is 100 ms. a fault is recorded only if the condition persists for more than a set minimum timeout. fault masking the faults can be masked to prevent triggering an interrupt on the fault pin. fault masking can be set using bits[6:0] of register 0x16. the mask can be set for the faults listed in table 18. table 18. fault masking fault ainxp ainxn short to battery yes yes short to micbias yes no short to ground yes yes short between positive and negative inputs yes yes open input yes yes when a fault mask bit is set, it is applied to all the channels. there is no individual fault mask available per channel using this bit. to mask individual channels, use the diag_mask[4:1] bits (bits[3:0] of register 0x15). diagnostics sequence the sequence shown in figure 23 is recommended for reading the faults reported by diagnostics. figure 23. diagnostics sequence normal fault event irq to system micro fault timeout irq to system micro fault timeout irq to system micro fault timeout irq to system micro fault timeout irq to system micro i 2 c sequence i 2 c sequence i 2 c sequence i 2 c sequence i 2 c sequence normal fault timeout ainx+/ ainx? fault pin i 2 c 10296-023
data sheet adau1977 rev. a | page 23 of 64 in the event of a fault on an input pin, the fault pin goes low or high depending on the setting of the irq_pol bit in register 0x15 to send an interrupt request to the system microcontroller. the system microcontroller responds to the interrupt request by communicating with the adau1977 via the i 2 c. the following is the typical interrupt service routine: 1. an interrupt request is generated from the adau1977 to the system microcontroller. 2. read register 0x11 through register 0x14. (it is recom- mended to read all four diagnostics status registers register 0x11 through register 0x14in one sequence. reading the registers as a single read may not report the status accurately.) 3. write register 0x15, bit 6 (the irq_reset bit). 4. wait for the fault timeout period to expire. 5. if the fault was temporary and did not persist, the interrupt service ends and the intermittent fault is ignored. if the fault persists, another interrupt request is generated from the adau1977 , and the user should continue on to step 6. 6. repeat step 2 through step 4 four times. 7. if after the fifth reading, the diagnostics still report the presence of a fault, the fault exists on the respective input and must be attended to. serial audio data output portsdata format the serial audio port comprises four pins: bclk, lrclk, sdataout1, and sdataout2. the adau1977 adc outputs are available on the sdataout1 and sdataout2 pins in serial format. the bclk and lrclk pins serve as the bit clock and frame clock, respectively. the port can be operated as master or slave and can be set either in stereo mode (2-channel mode) or in tdm multichannel mode. the supported popular audio formats are i 2 s, left justified (lj), right justified (rj). stereo mode in 2-channel or stereo mode, the sdataout1 outputs adc data for channel 1 and channel 2, and the sdatout2 outputs adc data for channel 3 and channel 4. figure 24 through figure 28 show the supported audio formats. figure 24. i 2 s audio format figure 25. lj audio format figure 26. rj audio format bclk lrclk sdataout1 (i 2 s mode) sdataout2 (i 2 s mode) notes 1. sai = 0. 2. sdata_fmt = 0 (i 2 s). channel 1 channel 2 8 to 32 bclks 8 to 32 bclks channel 3 channel 4 10296-024 bclk lrclk sdataout1 (lj mode) sdataout2 (lj mode) channel 1 channel 2 channel 3 channel 4 10296-025 notes 1. sdata_fmt = 1 (lj). bclk lrclk sdataout1 (rj mode) sdataout2 (rj mode) channel 1 channel 2 channel 3 channel 4 10296-026 notes 1. sdata_fmt = 2 (rj, 24-bit).
adau1977 data sheet rev. a | page 24 of 64 tdm mode r egister 0x 05 thr ough register 0x 08 provide programmability for the tdm mode. the tdm slot width, data width, and channel assignment , as well as the pin used to output the data , are programmable. by default , serial data is output on the sdataout1 pin ; however, the sdata_sel bit (bit 7 of register 0x0 6 ) can be used to change t he setting so that serial data is output from the sdataout 2 pin . the tdm mode supports 2 , 4 , 8 , or 16 channels. the adau1977 outputs four channels of data in the assigned slots ( figure 29 shows the data sl ot assignments) . during the unused slots , the output pin goes high - z so that the same data line can be shared with other devices on the tdm bus. the tdm port can be operated as either a master or a slave . in master mode , the bclk and lrclk are output fro m the adau1977 , whereas in slave mode , the bclk and lrclk pins are set to receive the clock from the master in the system. both the non pulse and pulse modes are supported. in non pulse mode , the lrclk signal is typically 50% of the duty cycle , whereas in pulse mode , the lrclk signal must be at least one bclk wide (s ee figure 27 and figure 28) . figure 27 . tdm nonpulse mode audio format figure 28 . tdm pulse mode audio format bclk lrclk sdata i 2 s sdata lj channel 1 channel 1 channel 2 channel n channel 2 channel n 10296-027 32/24/16 bclks 8 to 32 bclks 8 to 32 bclks 8 to 32 bclks 8 to 32 bclks 8 to 32 bclks 8 to 32 bclks 32/24/16 bclks 32/24/16 bclks sdata i 2 s channel 1 channel 2 channel n 24 or 16 bclks 24 or 16 bclks 24 or 16 bclks notes 1. sai = 001 (2 channels), 010 (4 channels), 011 (8 channels), 100 (16 channels). 2. sdata_fmt = 00 (i 2 s), 01 (lj), 10 (rj, 24-bit), 11 (rj, 16-bit). 3. bclk_edge = 0. 4. lrclk_mode = 0. 5. slot_width = 00 (32 bclks), 01 (24 bclks), 10 (16 bclks). bclk lrclk sdata i 2 s sdata lj channel 1 channel 1 channel 2 channel n channel 2 channel n 10296-028 32/24/16 bclks 8 to 32 bclks 8 to 32 bclks 8 to 32 bclks 8 to 32 bclks 8 to 32 bclks 8 to 32 bclks 32/24/16 bclks 32/24/16 bclks sdata i 2 s channel 1 channel 2 channel n 24 or 16 bclks 24 or 16 bclks 24 or 16 bclks notes 1. sai = 001 (2 channels), 010 (4 channels), 011 (8 channels), 100 (16 channels) 2. sdata_fmt = 00 (i 2 s), 01 (lj), 10 (rj, 24-bit), 11 (rj, 16-bit) 3. bclk_edge = 0 4. lrclk_mode = 1 5. slot_width = 00 (32 bclks), 01 (24 bclks), 10 (16 bclks)
data sheet adau1977 rev. a | page 25 of 64 figure 29. tdm mode slot assignment number of bclk cycles = (number of bclks/slot) number of slots slot2 slot1 slot1 slot2 slot3 slot4 slot1 slot2 slot3 slot4 slot5 slot6 slot7 slot8 slot1 slot2 slot3 slot4 slot5 slot6 slot7 slot8 slot 9 slot10 slot11 slot12 slot13 slot14 slot15 slot16 lrclk bclk sdataoutx-tdm2 sdataoutx-tdm4 sdataoutx-tdm8 sdataoutx-tdm16 data width 16/24 bits slot width 16/24/32bits high-z high-z 10296-029
adau1977 data sheet rev. a | page 26 of 64 the bit clock frequency depends on the sample rate, the slot width , and the number of bit clocks per slot. table 19 can be used to calculate the bclk frequency. the sample rate (f s ) can range from 8 khz up to 192 khz . h owever, in master mode , the maximum bit clock frequency (bclk) is 24.576 mhz. for example , for a sample rate of 192 khz, 128 f s is the maximum possible bclk frequency . therefore , only 128 bit clock cycles are available per tdm frame. there are two options in this case : either operat e with a 32- bit data width in tdm4 or operat e with a 16 - bit data width in tdm8. in slave mode , this limitation does not exist because the bit clock and frame clock are fed to the adau1977 . various combinations of bclk frequency and mode are available , but care must be taken to choose the combination that is most suitable for the application. connection options figure 30 through figure 34 show the available options for connecting the serial audio port in i 2 s or tdm mode. in tdm mode , it is recommended to include the pull - down resistor on the data signal to prevent the line from floating when the sdat a outx pin of adau1977 goes high - z during an inactive period. the resistor value should be such that no more than 2 ma is drawn from the sdataoutx pin. although t he resistor value is typically in the range of 10 k ? to 47 k ? , the appropriate resistor value depend s on the devices on the data bus. table 19. bit clock frequency tdm mode bclk frequency mode 16 bit clocks per slot 24 bit clocks per slot 32 bit clocks per slot tdm2 32 f s 48 f s 64 f s tdm4 64 f s 96 f s 128 f s tdm8 128 f s 192 f s 256 f s tdm16 256 f s 384 f s 512 f s figure 30 . serial port connection option 1 i 2 s/lj/ rj mode, adau1977 master figure 31 . serial port connection option 2 i 2 s/lj/ rj mode, adau1977 slave dsp slave master adau1977 bclk lrclk sdataout1 sdataout2 10296-030 dsp master slave adau1977 bclk lrclk sdataout1 sdataout2 10296-033
data sheet adau1977 rev. a | page 27 of 64 figure 32 . serial port connection option 3 tdm mode, adau1977 master figure 33 . serial port connection option 4 tdm mode, second adc master figure 34 . serial port connection option 5 tdm mode, dsp master dsp slave master adau1977 bclk lrclk sdataoutx slave adau1977 or similiar adc bclk lrclk sdataoutx 10296-031 dsp slave slave adau1977 bclk lrclk sdataoutx master adau1977 or similiar adc bclk lrclk sdataoutx 10296-034 dsp master slave adau1977 bclk lrclk sdataoutx slave adau1977 or similiar adc bclk lrclk sdataoutx 10296-032
adau1977 data sheet rev. a | page 28 of 64 control ports the adau1977 control port allows t wo modes of operation either 2 - wire i 2 c mode or 4 - wire spi mode that are used for s etting the internal registers of the part . both the i 2 c and spi modes allow read and write capability of the registers. all the registers are eight bit s wide. the registers start at address 0x00 and end at address 0x 1a . the control port in both i 2 c and spi modes is slave only and , therefore, requires the master in the system to operate . the registers can be accessed with or without the master clock to the part. however , to operate the pll, serial audio ports, and boost converter , the master clock is nec essary. by default, the adau1977 operates in i 2 c mode , but the part can be put into spi mode by pulling the clatch pin low three times. the control port pins are multifunctional, depending on the mode in which the part is operating. table 20 describes the control p ort pin functions in both modes . table 20 . control port pin functions i 2 c mode spi mode pin no. pin name pin functions pin type pin functions pin type 17 sda/cout sda: data i/o cout: output data o 18 scl/cclk scl: clock i cclk: input clock i 19 addr0/ clatch i 2 c device address bit 0 i clatch : input i 20 addr1/cin i 2 c device address bit 1 i cin: input data i
data sheet adau1977 rev. a | page 29 of 64 i 2 c mode the adau1977 supports a 2 - wire serial (i 2 c - compatible) bus protocol . two pins serial da ta (sda) and serial clock (scl) are used to communicate with t he system i 2 c master controller. in i 2 c mode, the adau1977 is always a slave on the bus, meaning that it cannot initiate a data transfer. each slav e device on the i 2 c bus is recognized by a unique device address. the device address and r/ w byte for the adau1977 are sho wn in table 21 . the address resides in the first seven bits of the i 2 c write. bit 7 and bit 6 of the i 2 c address for the adau1977 are set by the levels on the addr1 and addr0 pins. the lsb of the first i 2 c byte ( the r/ w bit ) from the master iden tifies whether it is a read or write operation. logic level 1 in lsb corresponds to a read operation , and logic level 0 corresponds to a write operation. table 21. adau1977 i 2 c first byte format bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 addr1 addr0 1 0 0 0 1 r/ w the first seven bits of the i 2 c chip address for the adau1977 are xx10001. bit 0 and bit 1 of the address byte can be set using the addr1 and addr0 pins to set the chip address to the desired value. the 7 - bit i 2 c device address can be set to one of four possible options using the addr1 and addr0 pins: ? i 2 c device address 0010001 (0x11) ? i 2 c device address 0110001 (0x31) ? i 2 c device address 1010001 (0x51) ? i 2 c device address 1110001 (0x71) in i 2 c mode, b o th t he sda and scl pins require that an appropriate pull - up resistor be connected to iovdd . the voltage on these signal lines should not exceed the voltage on the iovdd pin . figure 46 shows a typical connection diagram for the i 2 c mode. the value of the pull - up resistor for the sda or scl pin can be calculated as follows. minimum r pull up = ( iovdd C v il )/ i sink where : iovdd is the i / o supply voltage , typically ranging from 1.8 v up to 3.3 v. v il is the maximum voltage at logic level 0 (that is, 0.4 v , as per the i 2 c specifications ) . i sink is the current sink capability of the i/o pin. t he sda pin can sink 2 ma current ; therefore, the minimum value of r pull up for an iovdd of 3.3 v is 1.5 k ? . depending on the capacitance of the board , the speed of the bus can be restricted to meet the rise time and fall time specifications. for fast mode with a bit rate time of around 1 mbps, the rise time must be less than 550 ns . use t he following equation to determine whether the rise time specification can be met : t = 0.847 3 r pull up c board . to meet the 300 ns rise time requirement , the c board must be less than 236 p f. for the scl pin , the calculation s depend on the current sink capability of the i 2 c master used in the system. addressing initially, each device on the i 2 c bus is in an idle state and monitors the sda and scl lines for a start condition and the proper address. the i 2 c master initiates a data transfer by establishing a start condition, defined by a high - to - low transition on sda while scl remains high. this indicates that an addr ess/ data stream follows. all devices on the bus respond to the start condition and acquire the next eight bits from the master (the 7 - bit address plus the r/ w bit) msb first. the master sends the 7 - bit device address with the read/write bit to all the slaves on the bus. the device with the matching address responds by pulling the data line (sda) low during the ninth clock pulse. this ninth bit is known as an acknowledge bit. all other devices withdraw from the bus at this point and return to the idle condition. the r/ w bit determine s the direction of the data. a logic 0 on the lsb of the first byte means that the master is to write information to the slave , whereas a logic 1 means that the master is to read information from the slave after writing the address and repeating the start address. a data transf er takes place until a master initiates a stop condition. a stop condition occurs when sda transitions from low to high while scl is held high . stop and start conditions can be detected at any stage during the data transfer. if these conditions are assert ed out of sequence during normal read and write operations, the adau1977 immediately jumps to the idle condition.
adau1977 data sheet rev. a | page 30 of 64 figure 35. i 2 c write to adau1977 single byte figure 36. i 2 c read from adau1977 single byte 0 1 2 3 4 5 6 7 8 9 101112131415161718192021222324252627 addr1 addr0 1 0 0 0 1 start stop scl sd a first byte (device address) second byte (register address) third byte (data) r/w 10296-035 ack adau1977 ack adau1977 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 addr1 addr0 1 0 0 0 1 scl sd a third byte (device address) data byte from adau1977 r/w 10296-036 0123456789101112131415161718 addr1 addr0 1 0 0 0 1 start scl sd a first byte (device address) second byte (register address) r/w no ack stop ack adau1977 ack adau1977 ack adau1977 repeat start
data sheet adau1977 rev. a | page 31 of 64 i 2 c read and write operations figure 37 sh ows the format of a single - word write operation. every ninth clock pulse, the adau1977 issues an acknowledge by pulling sda low. figure 38 shows the format of a burst mode write sequence. this figure shows an example of a write to sequential single - byte registers. the adau1977 increments its address register after every byte because the requested address corresponds to a register or memory area with a 1 - byte word length. figure 39 shows the format of a single - word read operation. note that the first r/ w bit is 0, indicating a write operation. this is because the address still needs to be written to set up the internal address. after the adau1977 acknowledges the receipt of the address, the master must issue a repeated start command followed by the chip address byte with the r/ w bit set to 1 (read). this causes the adau1977 sda to reverse and begin driving data back to the master. the master then responds every ninth pulse with an acknowledge pulse to the adau1977 . figure 40 shows the format of a burst mode read sequence. this figu re shows an example of a read from sequential single - byte registers. the adau1977 increments its address registers after every byte because the adau1977 uses an 8 - bit register address . figure 37 to figure 40 use the following abbreviations: s = start bit p = stop bit am = acknowledge by master as = acknowledge by slave figure 37 . single - word i 2 c write format figure 38 . burst mode i 2 c write format figure 39 . single - word i 2 c read format figure 40 . burst mode i 2 c read format s chi p address, r/w = 0 as dat a byte as p register address 8 bits 10296-037 s chi p address, r/w = 0 as as as register address 8 bits dat a byte 1 dat a byte 2 dat a byte 3 dat a byte 4 as as as p ... chi p address, r/w = 0 10296-038 d at a byte 1 s chi p address, r/w = 0 as as p register address 8 bits chi p address, r/w = 1 as s 10296-039 dat a byte 1 s chi p address, r/w = 0 am register address 8 bits s as as as dat a byte 2 am ... p chi p address, r/w = 1 10296-040
adau1977 data sheet rev. a | page 32 of 64 spi mode by default, the adau1977 is in i 2 c mode . to invoke spi control mode , pull clatch low three times. this can be done by per - forming three dummy writes to the spi port (the adau197 7 does not acknowledge these three writes ; s ee figure 41) . b eginning with the fourth spi write, data can be written to or read from the device . the adau1977 can be taken out of spi mode only by a full reset initiated by power cycling the device. the spi port uses a 4 - wire interface, consisting of the clatch , cclk, c in , and cout signals, and it is always a slave port. the clatch signal should go low at the beginning of a trans - action and high at the end of a transaction. the cclk signal latches c in on a low - t o - high transition. cout data is shifted out of the adau1977 on the falling edge of cclk and should be clocked into a receiving device, such as a microcontroller, on the cclk rising edge. the c in signal carries the serial input data, and the cout signal carries the serial output data. the cout signal remains t ri state d until a read operation is requested. this allows direct connection to other spi - co mpatible peripheral cout ports for sharing the same system controller port . all spi transactions have the same basic format shown in table 24. a timing diagram is shown in figure 3 . all data should be written msb first. chip addr ess r/ w the lsb of the first byte of an spi transaction is a r/ w bit. this bit determines whether the communication is a read (logic level 1) or a write (logic level 0). this format is shown in table 22. table 22 . adau1977 spi address and r/ w byte format bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0 0 0 0 0 0 0 r/ w register address the 8 - bit address word is decoded to a location in one of the registers. this address is the location of the appropriate register. data bytes the number of data bytes varies according to the register being accessed. during a burst mode write, an initial register address is written followe d by a continuous sequence of data for consecutive register locations. a sample timing diagram for a single - word spi write operation to a register is shown in figure 42 . a sample timing diagram of a single - word spi read operation is shown in figure 43 . th e cout pin goes from being high - z to being driven at the beginning of byte 3. in this example, byte 0 to byte 1 contain the device address , the r/ w bit, and the register address to be read. s ubsequent bytes carry the data from the device. standalone mode the adau1977 can also be operated in stand alone mode. however , in standalone mode , the boost converter, mic rophone bias, and diagnostic s blocks are powered down. to set the part in stand alone mode , pull the sa_mode pin to iovdd. in this mode , some pins change functionality to provide more flexibility (see table 23 for more information). table 23. pin functionality in standalone mode pin function setting description addr0 0 i 2 s sai format 1 tdm modes , determined by the sdata out 2 pin addr1 0 master mode sai 1 slave mode sai sda 0 mclk = 256 f s , pll on 1 mclk = 384 f s , pll on scl 0 48 khz sample rate 1 96 khz sample rate sdata out 2 0 tdm4 lrclk pulse 1 tdm8 lrclk pulse fault 0 slot 1 to slot 4 in tdm8 1 slot 5 to slot 8 in tdm8 if set for tdm8 mode , the fault pin is used as an input for assigning the adc data slot to prevent collision with other data on tdm bus. table 24 . generic control word format byte 0 byte 1 byte 2 byte 3 1 device address [6:0], r/ w register address [7:0] data [7:0] data [7:0] 1 continues to end of data .
data sheet adau1977 rev. a | page 33 of 64 figure 41. spi mode initial sequence figure 42. spi write to adau1977 clocking (single-word write mode) figure 43. spi read from adau1977 clocking (single-word read mode) figure 44. spi write to adau1977 (multiple bytes) figure 45. spi read from adau1977 (multiple bytes) 0 1 2 3 4 5 6 7 8 9 101112131415161718192021222324252627 clatch cclk cin 10296-041 012345678 910111213 14 15 16 17 18 19 20 21 22 23 24 25 clatch cclk cin 10296-042 register address byte device address (7 bits) r/w data byte 012345678 910111213 14 15 16 17 18 19 20 21 22 23 24 25 clatch cclk cin cout 10296-043 register addr ess byte device addr ess (7 bits) r/w data byte data byte from adau1977 register address byte data byte1 data byte2 device address byte data byte n ? 1 data byte n clatch cclk cin 10296-044 device address byte register address byte data byte2 data byte3 data byte1 data byte n ? 1 data byte n clatch cclk cin cout 10296-045
adau1977 data sheet rev. a | page 34 of 64 register summary table 25 is the control register summary. the registers can be accessed using the i 2 c control port or the spi control port. table 25 . adau1977 register summary reg name bits bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset rw 0x00 m_power [7:0] s_rst reserved pwup 0x00 rw 0x01 pll_control [7:0] pll_lock pll_mute reserved clk_s reserved mcs 0x41 rw 0x02 bst_control [7:0] bst_good fs_rate boost_sw_ freq ov_en boost_ov oc_en boost_oc 0x4a rw 0x03 mb_bst_control [7:0] mb_volts mb_en boost_en mrcv boost_rcvr 0x7d rw 0x04 block_power_sai [7:0] lr_pol bclkedge ldo_en vref_en adc_en4 adc_en3 adc_en2 adc_en1 0x3f rw 0x05 sai_ctrl0 [7:0] sdata_fmt sai fs 0x02 rw 0x06 sai_ctrl1 [7:0] sdata_sel slot_width data_width lr_mode sai_msb bclkrate sai_ms 0x00 rw 0x07 sai_cmap12 [7:0] cmap_c2 cmap_c1 0x10 rw 0x08 sai_cmap34 [7:0] cmap_c4 cmap_c3 0x32 rw 0x09 sai_overtemp [7:0] sai_drv_c4 sai_drv_c3 sai_drv_c2 sai_drv_c1 drv_hiz ot_mcrv ot_rcvr ot 0xf0 rw 0x0a postadc_gain1 [7:0] padc_gain1 0xa0 rw 0x0b postadc_gain2 [7:0] padc_gain2 0xa0 rw 0x0c postadc_gain3 [7:0] padc_gain3 0xa0 rw 0x0d postadc_gain4 [7:0] padc_gain4 0xa0 rw 0x0e misc_control [7:0] sum_mode reserved mmute reserved dc_cal 0x02 rw 0x10 diag_control [7:0] reserved diag_en4 diag_en3 diag_en2 diag_en1 0x0f rw 0x11 diag_status1 [7:0] reserved mic_short1 mich_open1 mich_sb1 mich_sg1 mich_smb1 micl_sb1 micl_sg1 0x00 rw 0x12 diag_status2 [7:0] reserved mic_short2 mic_open2 mich_sb2 mich_sg2 mich_smb2 micl_sb2 micl_sg2 0x00 rw 0x13 diag_status3 [7:0] reserved mic_short3 mic_open3 mich_sb3 mich_sg3 mich_smb3 micl_sb3 micl_sg3 0x00 rw 0x14 diag_status4 [7:0] reserved mic_short4 mic_open4 mich_sb4 mich_sg4 mich_smb4 micl_sb4 micl_sg4 0x00 rw 0x15 diag_irq1 [7:0] reserved irq_reset irq_drive irq_pol diag_mask4 diag_mask3 diag_mask2 diag_mask1 0x20 rw 0x16 diag_irq2 [7:0] bst_fault_ mask mic_short_ mask mic_open_ mask mich_sb_ mask mich_sg_ mask reserved micl_sb_ mask micl_sg_ mask 0x00 rw 0x17 diag_adjust1 [7:0] sht_t_trip sht_m_trip sht_g_trip sht_b_trip 0x00 rw 0x18 diag_adjust2 [7:0] reserved fault_to reserved hyst_sm_en hyst_sg_en hyst_sb_en 0x20 rw 0x19 asdc_clip [7:0] reserved adc_clip4 adc_clip3 adc_clip2 adc_clip1 0x00 rw 0x1a dc_hpf_cal [7:0] dc_sub_c4 dc_sub_c3 dc_sub_c2 dc_sub_c1 dc_hpf_c4 dc_hpf_c3 dc_hpf_c2 dc_hpf_c1 0x00 rw
data sheet adau1977 rev. a | page 35 of 64 register details master power and sof t reset register address: 0x00, reset: 0x00, name: m_power the power management control register is used for enabling b oost regulator, microphone bias , pll, band gap reference, adc , and ldo r egulator . table 26 . bit descriptions for m_power bits bit name settings description reset access 7 s_rst software reset. the software reset reset s all internal circuitry and place s all control registers to their default state. it is not necessary to reset the adau1977 during a power -up or p ower - down cycle. 0x0 rw 0 normal operation 1 software reset [6:1] reserved reserved. 0x00 rw 0 pwup master power - up control. the master power - up control fully power s up or power s down the adau1977 . this must be set to 1 to power up the adau1977 . individual blocks can be powered down via their respective power control registers. 0x0 rw 0 full power - down 1 master power -up
adau1977 data sheet rev. a | page 36 of 64 pll control register address: 0x01, reset: 0x41, name: pll_control table 27 . bit descriptions for pll_control bits bit name settings description reset access 7 pll_lock pll lock s tatus. pll lock status bit. when one pll is locked. 0x0 r 0 pll not locked 1 pll locked 6 pll_mute pll unlock autom ute. when set to 1, mutes the adc output if pll becomes unlocked. 0x1 rw 0 no automatic mute on pll unlock 1 automatic mute with pll unlock 5 reserved reserved. 0x0 rw 4 clk_s pll clock source select. selecting input clock source for pll. 0x0 rw 0 mclk used for pll input 1 lrclk used for pll input ; only s upported for sample rates > 32 khz [2:0] mcs master clock select. mcs bits determine the frequency multiplication ratio of the pll. it must be set based on the input mclk frequency and sample rate. 0x1 rw 001 256 f s mclk for 32 k hz up to 48 khz (s ee the pll section for other sample rates ) 010 384 f s mclk for 32 khz up to 48 khz (s ee the pll section for other sample rates ) 011 512 f s mclk for 32 k hz up to 48 khz (s ee the pll section for other sample rates ) 100 768 f s mclk for 32 k hz up to 48 khz (s ee the pll section for other sample rates ) 000 128 f s mclk for 32 k hz up to 48 khz (s ee the pll section for other sample rates )
data sheet adau1977 rev. a | page 37 of 64 bits bit name settings description reset access 101 reserved 110 reserved 111 reserved dc - t o - dc boost converter control re gister address: 0x02, reset: 0x4a, name: bst_control table 28 . bit descriptions for bst_control bits bit name settings description reset access 7 bst_good boost converter output status. 0x0 r 0 boost converter output n ot stab i l i zed 1 boost convert er output good [6:5] fs_rate sample rate control for boost switching frequency. 0x2 rw 00 8 khz/16 khz/32 khz/64 khz/128 khz f s 01 11.025 khz/22.05 khz/44.1 khz/88.2 khz/176.4 khz f s 10 12 khz/24 khz/48 khz/96 khz/192 khz f s 11 reserved 4 boost_sw_freq boost regulator switching frequency. 0x0 rw 0 1.5 mhz switching frequency 1 3 mhz switching frequency 3 ov_en overvoltage fault protection enable. 0x1 rw 0 disable 1 enable 2 boost_ov boost converter over voltage fault status. 0x0 r 0 normal operation 1 overvoltage fault 1 oc_en overcurrent fault protection enable. 0x1 rw 0 disable 1 enable 0 boost_oc boost converter overcurrent fault status. 0x0 r 0 normal operation 1 boost overcurrent protection active
adau1977 data sheet rev. a | page 38 of 64 micbias and boost control re gister address: 0x03, reset: 0x7d, name: mb_bst_control table 29 . bit descriptions for mb_bst_control bits bit name settings description reset access [7:4] mb_volts micbias output voltage . 0x7 rw 0000 5.0 v 0001 5.5 v 0010 6.0 v 0011 6.5 v 0100 7.0 v 0101 7.5 v 0110 8.0 v 0111 8.5 v 1000 9.0 v 1001 reserved 1010 reserved 1011 reserved 1100 reserved 1101 reserved 1110 reserved 1111 reserved 3 mb_en micbias enable. 0x1 rw 0 micbias powered down 1 micbias enabled 2 boost_en boost enable. 0x1 rw 0 boost off 1 boost on 1 mrcv boost fault manual recovery. 0x0 w 0 normal operation 1 attempt manual boost fault recovery
data sheet adau1977 rev. a | page 39 of 64 bits bit name settings description reset access 0 boost_rcvr boost recovery mode. 0x1 rw 0 automatic fault recovery 1 manual fault recovery ; u se mrcv to recover block power control and se rial port control re gister address: 0x04, reset: 0x3f, name: block_power_sai table 30 . bit descriptions for block_power_sai bits bit name settings description reset access 7 lr_pol sets lrclk polarity . 0x0 rw 0 lrclk low then high 1 lrclk high then low 6 bclkedge sets the bit clock edge on which data changes. 0x0 rw 0 data changes on falling edge 1 data changes on rising edge 5 ldo_en ldo regulator enable. 0x1 rw 0 ldo powered down 1 ldo enabled 4 vref_en voltage reference enable. 0x1 rw 0 voltage reference powered down 1 voltage reference enabled 3 adc_en4 adc channel 3 enable. 0x1 rw 0 adc channel powered down 1 adc channel enabled 2 adc_en3 adc channel 3 enable. 0x1 rw 0 adc channel powered down 1 adc channel enabled 1 adc_en2 adc channel 2 enable. 0x1 rw 0 adc channel powered down 1 adc channel enabled 0 adc_en1 adc channel 1 enable. 0x1 rw 0 adc channel powered down 1 adc channel enabled
adau1977 data sheet rev. a | page 40 of 64 serial port control register1 address: 0x05, reset: 0x02, name: sai_ctrl0 table 31 . bit descriptions for sai_ctrl0 bits bit name settings description reset access [7:6] sdata_fmt serial data format. 0x0 rw 00 i 2 s data delayed from edge of lrclk by 1 bclk 01 left justified 10 right justified, 24 - bit data 11 right justified, 16 - bit data [5:3] sai serial port mode. 0x0 rw 000 stereo (i 2 s, lj, rj) 001 tdm2 010 tdm4 011 tdm8 100 tdm16 [2:0] fs sampling rate . 0x2 rw 000 8 khz to 12 khz 001 16 khz to 24 khz 010 32 khz to 48 khz 011 64 khz to 96 khz 100 128 khz to 192 khz
data sheet adau1977 rev. a | page 41 of 64 serial port control register2 address: 0x06, reset: 0x00, name: sai_ctrl1 table 32 . bit descriptions for sai_ctrl1 bits bit name settings description reset access 7 sdata_sel sdata outx pin selection in tdm4 or greater modes . 0x0 rw 0 sdata out 1 used for output 1 sdata out 2 used for output [6:5] slot_width number of bclks per slot in tdm mode. 0x0 rw 00 32 bclks per tdm slot 01 24 bclks per tdm slot 10 16 bclks per tdm slot 11 reserved 4 data_width output data bit width. 0x0 rw 0 24 - bit data 1 16 - bit data 3 lr_mode sets lrclk mode. 0x0 rw 0 50% duty cycle clock 1 pulse lrclk is a single bclk cycle wide pulse 2 sai_msb sets data to be input/output either msb or lsb first. 0x0 rw 0 msb first data 1 lsb first data 1 bclkrate sets the number of bit clock cycles per data channel generated when in master mode. 0x0 rw 0 32 bclks/channel 1 16 bclks/channel 0 sai_ms sets the serial port into master or slave mode. 0x0 rw 0 lrclk/bclk slave 1 lrclk/bclk master
adau1977 data sheet rev. a | page 42 of 64 channel mapping for output serial ports register address: 0x07, reset: 0x10, name: sai_cmap12 table 33 . bit descriptions for sai_cmap12 bits bit name settings description reset access [7:4] cmap_c2 adc channel 2 output mapping. 0x1 rw 0000 slot 1 for channel 0001 slot 2 for channel 0010 slot 3 for channel (on sdata out 2 in stereo modes) 0011 slot 4 for channel (on sdata out 2 in stereo modes) 0100 slot 5 for channel (tdm8+ only) 0101 slot 6 for channel (tdm8+ only) 0110 slot 7 for channel (tdm8+ only) 0111 slot 8 for channel (tdm8+ only) 1000 slot 9 for channel (tdm16 only) 1001 slot 10 for channel (tdm16 only) 1010 slot 11 for channel (tdm16 only) 1011 slot 12 for channel (tdm16 only) 1100 slot 13 for channel (tdm16 only) 1101 slot 14 for channel (tdm16 only) 1110 slot 15 for channel (tdm16 only) 1111 slot 16 for channel (tdm16 only)
data sheet adau1977 rev. a | page 43 of 64 bits bit name settings description reset access [3:0] cmap_c1 adc channel 1 output mapping. if c map is set to a slot that doesn t exist for a given serial mode, then that channel will not be driven. for example, if cmap is set to slot 9 and the serial format is i2s, then that channel will not be driven. if more than one channel is set to the same slo t , only the lowest channel number will be driven ; other channels will not be driven. 0x0 rw 0000 slot 1 for channel 0001 slot 2 for channel 0010 slot 3 for channel (on sdata out 2 in stereo modes) 0011 slot 4 for channel (on sdata out 2 in stereo modes) 0100 slot 5 for channel (tdm8+ only) 0101 slot 6 for channel (tdm8+ only) 0110 slot 7 for channel (tdm8+ only) 0111 slot 8 for channel (tdm8+ only) 1000 slot 9 for channel (tdm16 only) 1001 slot 10 for channel (tdm16 only) 1010 slot 11 for channel (tdm16 only) 1011 slot 12 for channel (tdm16 only) 1100 slot 13 for channel (tdm16 only) 1101 slot 14 for channel (tdm16 only) 1110 slot 15 for channel (tdm16 only) 1111 slot 16 for channel (tdm16 only)
adau1977 data sheet rev. a | page 44 of 64 channel mapping for output serial ports register address: 0x08, reset: 0x32, name: sai_cmap34 table 34 . bit descriptions for sai_cmap34 bits bit name settings description reset access [7:4] cmap_c4 adc channel 4 output mapping. 0x3 rw 0000 slot 1 for channel 0001 slot 2 for channel 0010 slot 3 for channel (on sdata out 2 in stereo modes) 0011 slot 4 for channel (on sdata out 2 in stereo modes) 0100 slot 5 for channel (tdm8+ only) 0101 slot 6 for channel (tdm8+ only) 0110 slot 7 for channel (tdm8+ only) 0111 slot 8 for channel (tdm8+ only) 1000 slot 9 for channel (tdm16 only) 1001 slot 10 for channel (tdm16 only) 1010 slot 11 for channel (tdm16 only) 1011 slot 12 for channel (tdm16 only) 1100 slot 13 for channel (tdm16 only) 1101 slot 14 for channel (tdm16 only) 1110 slot 15 for channel (tdm16 only) 1111 slot 16 for channel (tdm16 only)
data sheet adau1977 rev. a | page 45 of 64 bits bit name settings description reset access [3:0] cmap_c3 adc channel 3 output mapping. 0x2 rw 0000 slot 1 for channel 0001 slot 2 for channel 0010 slot 3 for channel (on sdata out 2 in stereo modes) 0011 slot 4 for channel (on sdata out 2 in stereo modes) 0100 slot 5 for channel (tdm8+ only) 0101 slot 6 for channel (tdm8+ only) 0110 slot 7 for channel (tdm8+ only) 0111 slot 8 for channel (tdm8+ only) 1000 slot 9 for channel (tdm16 only) 1001 slot 10 for channel (tdm16 only) 1010 slot 11 for channel (tdm16 only) 1011 slot 12 for channel (tdm16 only) 1100 slot 13 for channel (tdm16 only) 1101 slot 14 for channel (tdm16 only) 1110 slot 15 for channel (tdm16 only) 1111 slot 16 for channel (tdm16 only)
adau1977 data sheet rev. a | page 46 of 64 serial output drive and overtemperature protection control register address: 0x09, reset: 0xf0, name: sai_overtemp table 35 . bit descriptions for sai_overtemp bits bit name settings description reset access 7 sai_drv_c4 channel 4 serial output drive enable. 0x1 rw 0 channel not driven on serial output port 1 channel driven on serial output port; slot determined by cmap 6 sai_drv_c3 channel 3 serial output drive enable. 0x1 rw 0 channel not driven on serial output port 1 channel driven on serial output port; slot determined by cmap 5 sai_drv_c2 channel 2 serial output drive enable. 0x1 rw 0 channel not driven on serial output port 1 channel driven on serial output port; slot determined by cmap 4 sai_drv_c1 channel 1 serial output drive enable. 0x1 rw 0 channel not driven on serial output port 1 channel driven on serial output port; slot determined by cmap 3 drv_hiz select whether to tristate unused sai channels or to actively drive these data slots. 0x0 rw 0 unused outputs driven low 1 unused outputs hi gh -z 2 ot_mcrv over t emperature manual recovery attempt. 0x0 w 0 normal operation 1 attempt manual overtemperature recovery 1 ot_rcvr over t emperature manual recovery. 0x0 rw 0 automatic recovery from overtemperature fault 1 manual recovery from overtemp erature fault, must set ot_mc r v register
data sheet adau1977 rev. a | page 47 of 64 bits bit name settings description reset access 0 ot overtemperature status. 0x0 r 0 normal operation 1 overtemperature fault post adc gain channe l 1 control register address: 0x0a, reset: 0xa0, name: postadc_gain1 table 36 . bit descriptions for postadc_gain1 bits bit name settings description reset access [7:0] padc_gain1 channel 1 post adc gain. 0xa0 rw 00000000 +60 db gain 00000001 +59.625 db gain 00000010 +59.25 db gain ... ... 10011111 +0.375 db gain 10100000 0 db gain 10100001 ? 0.375 db gain ... ... 11111110 ? 35.625 db gain 11111111 mute
adau1977 data sheet rev. a | page 48 of 64 post adc gain channe l 2 control register address: 0x0b, reset: 0xa0, name: postadc_gain2 table 37 . bit descriptions for postadc_gain2 bits bit name settings description reset access [7:0] padc_gain2 channel 2 post adc gain. 0xa0 rw 00000000 +60 db gain 00000001 +59.625 db gain 00000010 +59.25 db gain ... ... 10011111 +0.375 db gain 10100000 0 db gain 10100001 ? 0.375 db gain ... ... 11111110 ? 35.625 db gain 11111111 mute
data sheet adau1977 rev. a | page 49 of 64 post adc gain channe l 3 control register address: 0x0c, reset: 0xa0, name: postadc_gain3 table 38 . bit descriptions for postadc_gain3 bits bit name settings description reset access [7:0] padc_gain3 channel 3 post adc gain. 0xa0 rw 00000000 +60 db gain 00000001 +59.625 db gain 00000010 +59.25 db gain ... ... 10011111 +0.375 db gain 10100000 0 db gain 10100001 ? 0.375 db gain ... ... 11111110 ? 35.625 db gain 11111111 mute
adau1977 data sheet rev. a | page 50 of 64 post adc gain channe l 4 control register address: 0x0d, reset: 0xa0, name: postadc_gain4 table 39 . bit descriptions for postadc_gain4 bits bit name settings description reset access [7:0] padc_gain4 channel 4 post adc gain. 0xa0 rw 00000000 +60 db gain 00000001 +59.625 db gain 00000010 +59.25 db gain ... ... 10011111 +0.375 db gain 10100000 0 db gain 10100001 ? 0.375 db gain ... ... 11111110 ? 35.625 db gain 11111111 mute
data sheet adau1977 rev. a | page 51 of 64 hig h - pass filter and dc o ffset control regist er and master mute address: 0x0e, reset: 0x02, name: misc_control table 40 . bit descriptions for misc_control bits bit name settings description reset access [7:6] sum_mode channel summing mode control for higher snr. 0x0 rw 00 normal 4 - channel operation 01 2 - channel sum ming operation ( see the adc summing modes section ) 10 1 - channel sum ming operation ( see the adc summing modes section ) 11 reserved 5 reserved reserved. 0x0 rw 4 mmute master mute. 0x0 rw 0 normal operation 1 all channels muted [3:1] reserved reserved. 0x1 rw 0 dc_cal dc calibration enable. 0x0 rw 0 normal operation 1 perform dc calibration
adau1977 data sheet rev. a | page 52 of 64 diagnostics control register address: 0x10, reset: 0x0f, name: diag_control table 41 . bit descriptions for diag_control bits bit name settings description reset access [7:4] reserved reserved. 0x0 rw 3 diag_en4 diagnostics enable channel 4. 0x1 rw 0 diagnostics disabled 1 diagnostics enabled 2 diag_en3 diagnostics enable channel 3. 0x1 rw 0 diagnostics disabled 1 diagnostics enabled 1 diag_en2 diagnostics enable channel 2. 0x1 rw 0 diagnostics disabled 1 diagnostics enabled 0 diag_en1 diagnostics enable channel 1. 0x1 rw 0 diagnostics disabled 1 diagnostics enabled
data sheet adau1977 rev. a | page 53 of 64 diagnostics report register c hannel 1 address: 0x11, reset: 0x00, name: diag_status1 table 42 . bit descriptions for diag_status1 bits bit name settings description reset access 7 reserved reserved. 0x0 rw 6 mic_short1 mic terminals shorted. 0x0 r 0 normal operation 1 mic terminals shorted 5 mich_open1 mic open connection. 0x0 r 0 normal operation 1 mic open connection 4 mich_sb1 mic high shorted to supply. 0x0 r 0 normal operation 1 mic high shorted to supply 3 mich_sg1 mic high shorted to ground. 0x0 r 0 normal operation 1 mic high shorted to ground 2 mich_smb1 mic high shorted to micbias. 0x0 r 0 normal operation 1 mic high shorted to micbias 1 micl_sb1 mic low shorted to supply. 0x0 r 0 normal operation 1 mic low shorted to supply 0 micl_sg1 mic low shorted to ground. 0x0 r 0 normal operation 1 mic low shorted to ground
adau1977 data sheet rev. a | page 54 of 64 diagnostics report r egister channel 2 address: 0x12, reset: 0x00, name: diag_status2 table 43 . bit descriptions for diag_status2 bits bit name settings description reset access 7 reserved reserved . 0x0 rw 6 mic_short2 mic terminals shorted. 0x0 r 0 normal operation 1 mic terminals shorted 5 mic_open2 mic open connection. 0x0 r 0 normal operation 1 mic open connection 4 mich_sb2 mic high shorted to supply. 0x0 r 0 normal operation 1 mic high shorted to supply 3 mich_sg2 mic high shorted to ground. 0x0 r 0 normal operation 1 mic high shorted to ground 2 mich_smb2 mic high shorted to micbias. 0x0 r 0 normal operation 1 mic high shorted to micbias 1 micl_sb2 mic low shorted to supply. 0x0 r 0 normal operation 1 mic low shorted to supply 0 micl_sg2 mic low shorted to ground. 0x0 r 0 normal operation 1 mic low shorted to ground
data sheet adau1977 rev. a | page 55 of 64 diagnostics report r egister channel 3 address: 0x13, reset: 0x00, name: diag_status3 table 44 . bit descriptions for diag_status3 bits bit name settings description reset access 7 reserved reserved. 0x0 rw 6 mic_short3 mic terminals shorted. 0x0 r 0 normal operation 1 mic terminals shorted 5 mic_open3 mic open connection. 0x0 r 0 normal operation 1 mic open connection 4 mich_sb3 mic high shorted to supply. 0x0 r 0 normal operation 1 mic high shorted to supply 3 mich_sg3 mic high shorted to ground. 0x0 r 0 normal operation 1 mic high shorted to ground 2 mich_smb3 mic high shorted to micbias. 0x0 r 0 normal operation 1 mic high shorted to micbias 1 micl_sb3 mic low shorted to supply. 0x0 r 0 normal operation 1 mic low shorted to supply 0 micl_sg3 mic low shorted to ground. 0x0 r 0 normal operation 1 mic low shorted to ground
adau1977 data sheet rev. a | page 56 of 64 diagnostics report r egister channel 4 address: 0x14, reset: 0x00, name: diag_status4 table 45 . bit descriptions for diag_status4 bits bit name settings description reset access 7 reserved reserved . 0x0 rw 6 mic_short4 mic terminals shorted. 0x0 r 0 normal operation 1 mic terminals shorted 5 mic_open4 mic open connection. 0x0 r 0 normal operation 1 mic open connection 4 mich_sb4 mic high shorted to supply. 0x0 r 0 normal operation 1 mic high shorted to supply 3 mich_sg4 mic high shorted to ground. 0x0 r 0 normal operation 1 mic high shorted to ground 2 mich_smb4 mic high shorted to micbias. 0x0 r 0 normal operation 1 mic high shorted to micbias 1 micl_sb4 mic low shorted to supply. 0x0 r 0 normal operation 1 mic low shorted to supply 0 micl_sg4 mic low shorted to ground. 0x0 r 0 normal operation 1 mic low shorted to ground
data sheet adau1977 rev. a | page 57 of 64 diagnostics interrup t pin control regist er 1 address: 0x15, reset: 0x20, name: diag_irq1 table 46 . bit descriptions for diag_irq1 bits bit name settings description reset access 7 reserved reserved. 0x0 rw 6 irq_reset fault pin reset. 0x0 rw 0 normal operation 1 reset fault pin 5 irq_drive fault pin drive options. 0x1 rw 0 fault pin always driven 1 fault pin only driven during fault, otherwise hi gh - z 4 irq_pol fault pin polarity. 0x0 rw 0 faults set fault pin low 1 faults set fault pin high 3 diag_mask4 fault pin mask for all channel 4 faults. 0x0 rw 0 faults on channel 4 trigger fault pin 1 faults on channel 4 do not trigger fault pin 2 diag_mask3 fault pin mask for all channel 3 faults. 0x0 rw 0 faults on channel 3 trigger fault pin 1 faults on channel 3 do not trigger fault pin 1 diag_mask2 fault pin mask for all channel 2 faults. 0x0 rw 0 faults on channel 2 trigger fault pin 1 faults on channel 2 do not trigger fault pin 0 diag_mask1 fault pin mask for all channel 1 faults. 0x0 rw 0 faults on channel 1 trigger fault pin 1 faults on channel 1 do not trigger fault pin
adau1977 data sheet rev. a | page 58 of 64 diagnostics interrup t pin control regist er 2 address: 0x16, reset: 0x00, name: diag_irq2 table 47 . bit descriptions for diag_irq2 bits bit name settings description reset access 7 bst_fault_mask fau lt pin mask for boost faults. 0x0 rw 0 boost faults assert fau lt pin 1 boost faults do not assert fau lt pin 6 mic_short_mask fau lt pin mask for mic terminal short fault. 0x0 rw 0 faults trigger fau lt pin 1 fault s do not trigger fau lt pin 5 mic_open_mask fau lt pin mask for mic open connection fault. 0x0 rw 0 faults trigger fau lt pin 1 faults do not trigger fau lt pin 4 mich_sb_mask fau lt pin mask for mic high short to supply fault. 0x0 rw 0 faults trigger fau lt pin 1 faults do not trigger fau lt pin 3 mich_sg_mask fau lt pin mask for mic high short to ground fault. 0x0 rw 0 faults trigger fau lt pin 1 faults do not trigger fau lt pin 1 micl_sb_mask fau lt pin mask for mic low short to supply fault. 0x0 rw 0 faults trigger fau lt pin 1 faults do not trigger fau lt pin 0 micl_sg_mask fau lt pin mask for mic low short to ground fault. 0x0 rw 0 faults trigger fau lt pin 1 faults do not trigger fau lt pin
data sheet adau1977 rev. a | page 59 of 64 diagnostics adjustme nts register 1 address: 0x17, reset: 0x00, name: diag_adjust1 table 48. bit descriptions for diag_adjust1 bits bit name settings description reset access [7:6] sht_t_trip short fault to other terminal trip point adjust. 0x0 rw 00 0.465 micbias t o 0.535 micbias 01 0.483 micbias to 0.517 micbias 10 0.429 micbias to 0.571 micbias 11 reserved [5:4] sht_m_trip short fault to mic bias trip point adjust. 0x0 rw 00 0.95 micbias 01 0.9 micbias 10 0.85 micbias 11 0.975 micbias [3:2] sht_g_trip short fault to ground trip point adjust. 0x0 rw 00 0.2 vref 01 0.133 vref 10 0.1 vref 11 0.266 vref [1:0] sht_b_trip short fault to supply/battery trip point adjust. 0x0 rw 00 0.95 vbat 01 0.9 vbat 10 0.85 vbat 11 0.975 vbat
adau1977 data sheet rev. a | page 60 of 64 diagnostics adjustme nts register 2 address: 0x18, reset: 0x20, name: diag_adjust2 table 49 . bit descriptions for diag_adjust2 bits bit name settings description reset access [7:6] reserved reserved. 0x0 rw [5:4] fau lt_ to fault timeout adjust. 0x2 rw 00 no fault timeout period ( that is , the time that the fault needs to persist before being reported) 01 50 ms fault timeout period 10 100 ms fault timeout period (default) 11 150 ms fault timeout period 3 reserved reserved. 0x0 rw 2 hyst_sm_en hyster e sis short to micbias enable. 0x0 rw 0 disable 1 enable 1 hyst_sg_en hyster e sis short to ground enable. 0x0 rw 0 disable 1 enable 0 hyst_sb_en hyster e sis short to battery enable. 0x0 rw 0 disable 1 enable
data sheet adau1977 rev. a | page 61 of 64 adc clipping status register address: 0x19, reset: 0x00, name: asdc_clip table 50 . bit descriptions for asdc_clip bits bit name settings description reset access [7:4] reserved reserved. 0x0 rw 3 adc_clip4 adc channel 4 clip status. 0x0 r 0 normal operation 1 adc channel clipping 2 adc_clip3 adc channel 3 clip status. 0x0 r 0 normal operation 1 adc channel clipping 1 adc_clip2 adc channel 2 clip status. 0x0 r 0 normal operation 1 adc channel clipping 0 adc_clip1 adc channel 1 clip status. 0x0 r 0 normal operation 1 adc channel clipping
adau1977 data sheet rev. a | page 62 of 64 digital dc high - pass filter and cali bration register address: 0x1a, reset: 0x00, name: dc_hpf_cal table 51 . bit descriptions for dc_hpf_cal bits bit name settings description reset access 7 dc_sub_c4 channel 4 dc subtraction from calibration. 0x0 rw 0 no dc subtraction 1 dc value from dc calibration is subtracted 6 dc_sub_c3 channel 3 dc subtraction from calibration. 0x0 rw 0 no dc subtraction 1 dc value from dc calibration is subtracted 5 dc_sub_c2 channel 2 dc subtraction from calibration. 0x0 rw 0 no dc subtraction 1 dc value from dc calibration is subtracted 4 dc_sub_c1 channel 1 dc subtraction from calibration. 0x0 rw 0 no dc subtraction 1 dc value from dc calibration is subtracted 3 dc_hpf_c4 channel 4 dc high - pass filter enable. 0x0 rw 0 hpf off 1 hpf on 2 dc_hpf_c3 channel 3 dc high - pass filter enable. 0x0 rw 0 hpf off 1 hpf on 1 dc_hpf_c2 channel 2 dc high - pass filter enable. 0x0 rw 0 hpf off 1 hpf on 0 dc_hpf_c1 channel 1 dc high - pass filter enable. 0x0 rw 0 hpf off 1 hpf on
data sheet adau1977 rev. a | page 63 of 64 application s circuit figure 46 . typical application schematic two microphones, two line inputs, i 2 c and i 2 s mode i2c/spi contro l mic1 v ac = 2v diff c9 10f electro l ytic 1nf max mlcc c18 10f c19 0.1f c20 c21 r17 +3.3v ( a vdd2) c10 10f mlcc x7r 10f mlcc x7r c 1 1 0.1f c12 0.1f +3.3v c13 0.1f c14 0.1f 4.7h c15 0.1f r ext r9 r10 r 1 1 r12 r15 r16 c7 0.1f c16 10f mlcc x7r +14.4v c1 t o c8 = 1000pf r1 t o r4 ty p = 500? 0.1% r17 c20 c21 4.87k? 2200pf 39nf pl l input option lrclk mclk 1k? 390pf 5600pf notes 1. r9, r10, r15 = typica l 2k? for iovdd = 3.3 v , 1k? for 1.8 v . 2. r 1 1 through r14 used for setting the device in i 2 c mode. 3. r16 = typica l 47k? for iovdd = 3.3 v , 22k? for 1.8 v . 4. pl l loo p fi l ter: 5. for more inform a tion about calcul a ting the v alue of r ext , see the power-on reset sequence section. ain1+ micbias vboost_out sw a vdd1 a vdd3 a vdd2 dvdd iovdd lrclk bclk sd at aout1 t o ds p iovdd sd at aout2 scl/cclk sda/cout addr1/cin addr0/cl a tch f au l t pd/reset +1.8v or +3.3v vb a t (load dum p supressed) vboost_in mb_gnd vb a t a vddx agnd1 agnd3 a vdd2 a vdd1 pgnd a ttenu a t or 14db programmable gain decim a t or/hpf dc calibr a tion seria l audio port a vdd3 adc boost converter i out 50m a 3.3v t o 1.8v regul a t or adc adc adc agnd2 agndx agnd2 pgnd agnd1 agnd2 agnd3 dgnd vref mclkin pll_fi l t sa_mode c1 c2 c3 c4 c5 c6 c7 c8 r4 r2 r3 r13 r14 r1 ain1? ain2+ ain2? ain3+ ain3? diagnostics ain4+ ain4? mic2 v ac = 2v diff line1 v cm = 7 v , v ac = 10v diff line2 v cm = 7 v , v ac = 10v diff micro- controller 5v t o 9v prog bias 10296-046 adau1977 bg ref pl l
adau1977 data sheet rev. a | page 64 of 64 outline dimensions figure 47 . 40 - lead lead frame chip scale package [l fcs p _wq ] 6 mm 6 mm body, very very thin quad (cp - 40 - 14 ) dimensions shown in millimeters ordering guide model 1 , 2 temperature range package description package option adau1977 wbcpz C 40c to +105c 40 - lead l fcsp _wq cp - 40 - 14 adau1977 wbcp z -r 7 C 40c to +105c 40 - lead l fcsp _wq , 7 tape and reel cp -40 -14 ADAU1977WBCPZ -rl C 40c to +105c 40 - lead lfcsp _wq , 13 tape and reel cp -40 -14 eval - adau1977z evaluation board 1 z = rohs compliant part. 2 w = qualified for automotive applications. automotive products the ad au 197 7w models are available with controlled manufacturing to support the quality and reliability requirements of automotive applications. note that these automotive models may have specifications that differ from the commercial models; therefore, de signers should review the specifications section of this data sheet carefully. only the automotive grade products shown are available for use in automotive applicat ions. contact your local analog devices account representative for specific product ordering information and to obtain the specific automotive reliability reports for these models. 0.50 bsc bot t om view top view pin 1 indic a t or exposed pa d pin 1 indic a t or sea ting plane 0.05 max 0.02 nom 0.20 ref coplanarity 0.08 0.30 0.25 0.18 6.10 6.00 sq 5.90 0.80 0.75 0.70 for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. 0.45 0.40 0.35 0.25 min 4.05 3.90 sq 3.75 compliant to jedec standards mo-220- wjjd . 40 1 11 20 21 30 31 10 05-06-20 1 1- a ? 2013 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d10296 - 0 - 3/13(a)

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